NAND Package Branching Layout for Low-Reflection Memory Channels
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Solution Overview
Problem
Existing memory systems face challenges in maintaining high signal quality and downsizing semiconductor storage devices due to increased signal reflection and complexity in the connection terminals, particularly in NAND packages.
Innovation Solution
The memory system is configured with semiconductor memory chips and connection terminals optimized for one channel per channel, utilizing a branching structure that reduces signal reflection and allows for downsizing by integrating a relay component or using the package board for branching, thereby improving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple channels are integrated into a single semiconductor storage device, then functionality and storage capacity are improved, but signal reflection increases and signal quality deteriorates
Solution Approach 1:
The patent divides the connection terminals into separate groups for different channels (first channel connection terminals and second channel connection terminals). Each channel has its own dedicated terminals, preventing signal interference and reflection between channels. This segmentation maintains signal quality while enabling multi-channel functionality.
Solution Approach 2:
The package board acts as an intermediary component that provides separate connection paths for different channels. By using the package board as a mediator with distinct terminal groups for each channel, the patent enables multi-channel operation without signal degradation, as each channel's signals are transmitted through dedicated pathways.
2Adaptability or versatility
If connection terminals for multiple channels are integrated, then device functionality is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple channels into a single semiconductor storage device package, integrating first channel connection terminals and second channel connection terminals within the same device. This combining approach enables multi-channel functionality while maintaining a unified device structure, avoiding the need for separate devices for each channel.
Solution Approach 2:
The semiconductor storage device is designed with universal multi-functionality by incorporating both first channel and second channel connection terminals. The device can simultaneously handle multiple channels through its diversified terminal structure, allowing it to perform multiple functions (handling different channels) within a single unified component.
3Adaptability or versatility
If more connection terminals are added for additional channels, then storage capacity is improved, but downsizing becomes more difficult
Solution Approach 1:
The patent utilizes the package board as an intermediate dimension to accommodate multiple channel connection terminals. By extending the connection architecture into the package board layer, the design can support additional channels without proportionally increasing the chip area, as terminals are distributed across different layers and dimensions of the package structure.
Data Source
AI summary
A memory system according to an embodiment includes a first board, a control circuit, and a semiconductor storage device. The semiconductor storage device includes a second board, a plurality of semiconductor memory chips, and a plurality of connection terminals. Each of the plurality of semiconductor memory chips includes only a plurality of first terminals for one channel configured of a predetermined number of terminals. The plurality of first terminals serve as terminals capable of transferring data signals or timing signals. The plurality of connection terminals include only a plurality of second terminals for one channel configured of the predetermined number of terminals. The plurality of second terminals serve as terminals capable of transferring the data signals or the timing signals.