NAND Memory Pad Layout Without Source Line Overlap
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Solution Overview
Problem
Existing NAND flash memory devices face challenges in optimizing the structure of the memory cell array to enhance data storage capacity and reliability while minimizing the overlap between the source line and pad areas, which can lead to electrical interference and manufacturing inefficiencies.
Innovation Solution
The memory device incorporates a structure where the source line in the memory cell array is designed such that it does not overlap with the pad area, with an insulating film embedded in this region to prevent electrical interference, and a layer stack with alternating conductive and insulating layers to facilitate efficient wiring connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the source line is extended to cover the pad area for simplified wiring, then wiring complexity is reduced, but electrical interference between the source line and pad increases
Solution Approach 1:
The source line is extracted from the pad area by intentionally creating a gap or discontinuity in the source line structure where it would otherwise overlap with the pad. This removes the harmful electrical interference while maintaining the simplified wiring layout in other regions.
Solution Approach 2:
The source line structure is made non-uniform by introducing a localized gap specifically in the region overlapping with the pad, while maintaining continuous structure in other regions. This local modification eliminates electrical interference without affecting the overall wiring simplicity.
2Quantity of substance
If the memory cell array structure is optimized to increase storage capacity, then data storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The source line gap is designed and positioned in advance during the planning stage, with predetermined dimensions and locations that align with the pad structure. This preliminary design allows for standardized manufacturing processes and reduces the need for high-precision adjustments during fabrication.
Solution Approach 2:
The source line width, gap size, and positioning parameters are optimized to achieve an balance between storage capacity and manufacturability. By carefully selecting these parameters, the design achieves high density while remaining compatible with standard manufacturing capabilities.
3Area of stationary object
If the source line overlaps with the pad area, then area utilization is improved, but electrical interference and manufacturing difficulty increase
Solution Approach 1:
The source line is extracted from the pad area by intentionally creating a gap or discontinuity in the source line structure where it would otherwise overlap with the pad. This removes the harmful electrical interference while maintaining the simplified wiring layout in other regions.
Solution Approach 2:
Instead of completely eliminating source line coverage in the pad region, only the problematic overlapping portion is removed by creating a gap of appropriate size. This partial removal maintains area utilization efficiency while eliminating manufacturing and electrical interference issues.
Data Source
AI summary
A memory device according to an embodiment includes a bonding surface. The memory device includes a substrate, first and second circuit layers, and a wiring layer. The substrate has first and second areas. The first circuit layer includes a CMOS circuit. The second circuit layer is provided above the bonding surface. The wiring layer is provided above the second circuit layer. The wiring layer includes a pad electrically connected to the CMOS circuit via the second circuit layer. The second circuit layer includes a layer stack. The layer stack includes, in the first area, first insulating layers and first conductive layers alternately stacked and includes, in the second area, the first insulating layers and the first conductive layers or first members alternately stacked. The pad has a portion overlapping with the layer stack and does not have a portion overlapping with a source line.