3D NAND Pad Tier Layout for Logic-Region Die Area Reduction
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Solution Overview
Problem
Conventional bond pad configurations in non-volatile memory devices, such as 3D NAND Flash memory devices, hinder performance improvements and reduce feature size reductions due to their design limitations.
Innovation Solution
The proposed solution involves a microelectronic device design with a conductive pad tier configuration, where first conductive pads are positioned outside the logic region and second conductive pads are placed within the logic region, allowing for improved electrical connectivity and reduced size without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bond pad configurations are used, then manufacturing simplicity is maintained, but device performance is hampered and feature size reduction is impeded
Solution Approach 1:
The pad structure is segmented into multiple functional layers: a first conductive pad layer for electrical connection, a second conductive pad layer for additional connectivity, and an insulative material layer for isolation. This segmentation allows each layer to perform its specific function optimally, improving device performance while maintaining manufacturing feasibility through standardized multi-layer fabrication processes
Solution Approach 2:
The invention transitions from conventional two-dimensional planar bond pads to a three-dimensional multi-layer pad structure. By stacking conductive pad layers vertically and using insulative materials to separate them, the design utilizes the vertical dimension to increase connectivity options and improve electrical performance without consuming additional horizontal die area, thereby enabling feature size reduction
2Area of stationary object
If bond pad size is reduced to increase packaging density, then packaging density improves, but manufacturing precision requirements increase
Solution Approach 1:
The multi-layer pad structure segments the electrical connection function across multiple layers, allowing each individual pad layer to be smaller while collectively providing sufficient connectivity. The insulative material layers provide clear boundaries and isolation, making it easier to align smaller pad features with precise manufacturing tolerances
Solution Approach 2:
The insulative material layers act as intermediaries between the conductive pad layers, providing physical separation and alignment references. These insulative layers can be used as etch stop layers or alignment markers during fabrication, reducing the precision requirements for aligning the smaller conductive pad features across multiple layers
Data Source
AI summary
A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.