NAND Page-Buffer Caching for Three-Dimensional Read-Disturbance Reduction
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Solution Overview
Problem
The increase in storage density in three-dimensional memories leads to increased data read problems, particularly Read Disturb (RD), which affects the reliability of NAND memory due to shifting threshold voltage distributions and higher error bit counts during read operations.
Innovation Solution
A memory system design that includes a memory controller configured to read data from a page buffer in response to consecutive read requests with related logical addresses, reducing the need for repeated read operations on the memory cell array and minimizing read disturbance by utilizing the existing page buffer to store and retrieve data directly from it.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory structures are developed to increase storage density, then storage capacity is improved, but read disturbance increases
Solution Approach 1:
The patent applies preliminary action by pre-loading data into the page buffer during the first read operation. When a second read request comes for related data, the data is already available in the page buffer, eliminating the need for repeated read operations on the memory cell array and thus preventing read disturbance.
Solution Approach 2:
The page buffer serves as an intermediary between the memory controller and the memory cell array. Instead of directly reading from the memory cell array for every request, the system uses the page buffer as an intermediate storage that holds recently accessed data, reducing direct read operations on the array and minimizing read disturbance.
2Reliability
If repeated read operations are performed on memory cell array, then data retrieval is ensured, but read disturbance increases
Solution Approach 1:
The system performs preliminary action by reading and storing data in the page buffer during the first read operation. Subsequent read requests for related data can be satisfied from the page buffer without repeating operations on the memory cell array, thus ensuring data retrieval while avoiding repeated read disturbance.
Solution Approach 2:
The patent implements copying by creating a copy of the data in the page buffer during the first read operation. This copy allows subsequent read requests to access data from the buffer rather than repeatedly reading from the original memory cell array, reducing read disturbance while maintaining data availability.
3Reliability
If page buffer is used to store read data, then read disturbance is reduced, but additional hardware is required
Solution Approach 1:
The patent applies universality by making the page buffer serve multiple functions: it acts as both a buffer for read operations and a storage mechanism for reducing read disturbance. The existing page buffer infrastructure is utilized for this additional purpose, avoiding the need for separate dedicated hardware components.
Solution Approach 2:
The system implements self-service by utilizing the existing page buffer capacity to store read data, thereby reducing the need for additional hardware. The page buffer serves itself by expanding its functionality to hold data for subsequent read requests, eliminating the need for separate disturbance-reduction hardware.
Data Source
AI summary
Examples of the present disclosure disclose memory systems, methods of operating memory systems, electronic apparatuses, and computer readable mediums. The example memory system includes a memory and a memory controller. The memory includes a memory cell array and a peripheral circuit coupled with the memory cell array, the peripheral circuit including a page buffer. The memory controller is configured to: in response to a first read request including a first logical address, read data from the memory cell array, and store the read data through the page buffer, where the data includes all data stored in a physical page to which a first physical address corresponding to the first logical address points; and in response to a second read request including a second logical address, read data corresponding to the second logical address from the page buffer, where the second logical address is related to the first logical address.