NAND Flash Page Buffer Circuit Reducing Transistor Count
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory page buffers at low densities require a more effective circuit with fewer transistors to reduce chip size, as existing designs do not efficiently manage transistor count for smaller die sizes in devices like 64M bit, 128M bit, 256M bit, or 1G bit storage.
Innovation Solution
A page buffer circuit for NAND flash memory that includes a pre-charge switch, first switch, read switch, write switch, latch, data switch, and enable switch, operating through specific logic levels and signal controls to reduce transistor count while maintaining data integrity and programming functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional page buffer circuits are used in low-density NAND flash memory, then data storage and read/write operations can be performed, but the chip size becomes larger due to higher transistor count
Solution Approach 1:
The patent merges the functionality of multiple switches into fewer transistors by using shared control mechanisms. Specifically, the precharge switch and first switch share control signals and circuit paths, reducing the total transistor count while maintaining the ability to perform precharge and data transfer operations independently when needed.
Solution Approach 2:
The patent implements multi-functional switches that can operate in different modes depending on control signals. The first switch, for example, can function as a data transfer switch during write operations and as part of the precharge path during read operations, eliminating the need for dedicated separate switches for each function.
2Ease of manufacture
If the number of transistors is reduced to shrink chip size, then manufacturing cost decreases, but circuit functionality and reliability may be compromised
Solution Approach 1:
The patent uses dynamic control signals to enable different circuit paths based on operational mode. During write operations, control signals configure the circuit for data input and transfer; during read operations, the same circuit is reconfigured for precharge and sense operations. This dynamic reconfiguration allows a reduced transistor count to perform all necessary functions reliably.
Solution Approach 2:
The patent introduces control signals as intermediaries that coordinate the reduced number of switches to perform multiple functions. These control signals act as mediators that enable the same physical circuit elements to serve different purposes in different operational contexts, maintaining reliability without requiring additional transistors.
Data Source
AI summary
A page buffer for a NAND flash memory array includes a pre-charge switch, a first switch, a read switch, a write switch, a latch, and a data switch. The pre-charge switch is coupled between a supply node with a supply voltage and a bit line that is coupled to a selected cell of the NAND flash memory array. The first switch is coupled between the bit line and a data node. The read switch is coupled between the data node and an I/O node. The write switch is coupled between an inverse data node, which is out of phase with the data node, and the I/O node. The latch is coupled between the data node and the inverse data node. The data switch is coupled between the inverse data node and a first node. The enable switch is coupled between the first node and a ground.