NAND Flash Page Buffer Multi-Functional Latch Design
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Solution Overview
Problem
Conventional page buffers in NAND flash memory designs either lack the cache function during programming operations or require excessive die size due to the use of three latch circuits, making them inefficient for implementing the cache function with two latch circuits.
Innovation Solution
A page buffer design incorporating a first and second latch circuit, a bit line voltage supply circuit, and a verification circuit with multiple verification paths to facilitate both MSB and LSB programming operations while verifying programming states, allowing for efficient data transfer and verification without increasing die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If three latch circuits are used to implement cache function during programming operations, then the cache function is available, but the die size increases excessively
Solution Approach 1:
The second latch circuit is designed to perform multiple functions: it serves as a data latch during programming operations and simultaneously provides cache functionality. By making the latch circuit multi-functional, the patent eliminates the need for a separate third latch circuit dedicated to caching, thereby reducing die size while maintaining the cache function during both MSB and LSB programming operations
Solution Approach 2:
The patent merges the cache function with the existing latch circuits used for data storage. Specifically, the second latch circuit is configured to hold both programming data and cache data at different times, combining what would traditionally require separate circuits into a single integrated structure, thus reducing overall die size
2Area of stationary object
If conventional page buffer design with two latch circuits is used, then die size is reduced, but the cache function is prohibited during MSB programming operation
Solution Approach 1:
The latch circuits are designed with dynamic control signals that enable them to switch between different operational modes. The second latch circuit can dynamically function as a data latch during LSB programming and as a cache latch during MSB programming, allowing the cache function to be available during MSB operations while maintaining compact die size
Solution Approach 2:
The patent utilizes control signals (such as EN0, EN1, and other enable signals) to change the operational parameters of the latch circuits based on the programming mode. By adjusting these control parameters, the same hardware structure can provide cache functionality during different programming operations without requiring additional circuitry
3Area of stationary object
If programming operations are performed without cache function, then die size is reduced, but the time required for receiving input data and verifying programming states increases
Solution Approach 1:
The cache function stored in the second latch circuit allows data to be pre-loaded and held ready for programming operations. This preliminary action enables faster data availability during programming and verification, reducing the overall time required for receiving input data and verifying programming states while maintaining compact die size
Data Source
AI summary
A page buffer used in a NAND flash memory comprises a first latch circuit, a second latch circuit, a bit line voltage supply circuit and a verification circuit comprising a first verification path, a second verification path and a third verification path. The first latch circuit and the second latch circuit latch the data programmed into and read from the NAND flash memory. The bit line voltage supply circuit supplies bit line voltages to the corresponding bit line of the NAND flash memory. The verification circuit verifies the programming operations of the NAND flash memory. The first verification path is for the verification of a first LSB programming operation. The second verification path is for the verification of a second LSB programming operation before the first LSB programming operation is verified. The third verification path is for the verification of the second LSB programming operation after the first LSB programming operation is verified.