NAND Flash Page Buffer With Separate Pre-Charging Paths
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Solution Overview
Problem
Current NAND flash memory devices using current sensing schemes face challenges in controlling read current efficiently and maintaining process independency, leading to variations in read margins and reliability issues due to cell-to-cell interference and voltage threshold dependencies.
Innovation Solution
A page buffer circuit with separate pre-charging paths for bit-lines and sensing nodes, utilizing distinct voltage sources and switching circuits to control pre-charging and evaluation periods, allowing for precise current sensing and reduced read current without compromising reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current sensing scheme is used to read data from NAND flash memory, then read speed and capacity are improved, but read current control precision deteriorates and process independency is lost
Solution Approach 1:
The patent divides the pre-charging operation into two separate paths: one path (first pre-charging path) charges the bit-line from the first voltage source, and another path (second pre-charging path) charges the sensing node from the second voltage source. This segmentation allows independent control of voltage levels for bit-line and sensing node, enabling precise control of read current while maintaining high read speed through efficient parallel charging paths.
2Ease of operation
If conventional current sensing is used, then read operation is simplified, but read margins vary due to cell-to-cell interference and voltage threshold dependencies
Solution Approach 1:
The patent applies different voltage levels to different parts of the sensing circuit: the bit-line receives a first voltage level from the first voltage source, while the sensing node receives a second voltage level from the second voltage source. This local quality differentiation allows the sensing circuit to compensate for cell-to-cell interference and voltage threshold variations, improving read margins while maintaining operational simplicity through automated voltage management.
3Measurement precision
If read current is increased to improve sensing accuracy, then measurement precision is improved, but energy consumption and reliability issues increase
Solution Approach 1:
The patent changes the voltage parameters by providing different voltage levels to the bit-line and sensing node through separate voltage sources. This parameter differentiation enables accurate sensing with lower read current by creating an optimized voltage differential across the memory cell during read operation, thereby reducing energy consumption while maintaining or improving sensing accuracy compared to conventional uniform voltage approaches.
Data Source
AI summary
Disclosed herein is a NAND flash memory comprising a bit-line and a page buffer, the page buffer comprising: a first switching circuit arranged between a first node and the bit-line; a third switching circuit arranged between the first node and a sensing node and configured to discharge the sensing node during an evaluation period, a pre-charging period preceding the evaluation period; and a fourth switching circuit configured to provide a first pre-charging path to the bit-line through the first node and the first switching circuit from a first voltage source during the pre-charging period, wherein the sensing node is configured to be charged through a second pre-charging path during the pre-charging period, and the second pre-charging path is separated from the first pre-charging path by the third switching circuit during the pre-charging period.