3D NAND Page Buffer Sensing Circuit for Fast Verify Operations
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Solution Overview
Problem
Current 3D NAND flash memory programming methods require multiple verify operations at different voltages, necessitating multiple precharging and sensing steps, which increases programming time and complexity.
Innovation Solution
The proposed method involves a page buffer with a first sensing circuit and a dynamic storage circuit, where initial verification information is transmitted to the sensing node, and the first verification information is cleared from the sensing circuit, allowing the first sensing circuit to latch second verification information, enabling a single complete sensing at a consistent verify voltage for 4BL scheme operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple verify operations at different voltages are performed, then verification accuracy is improved, but programming time increases
Solution Approach 1:
The sensing node is precharged to a first potential before the first verify operation, and then maintained at a second potential during the second verify operation. This preliminary charging action allows the sensing node to be ready for multiple verification stages without requiring repeated precharging, thereby reducing programming time while maintaining verification accuracy across multiple voltage levels.
Solution Approach 2:
The sensing node potential is continuously adjusted from the first potential to the second potential without interrupting the verification process. This continuous action allows both verify operations at different voltages to be performed in sequence without stopping the useful action of verification, thus improving programming speed while preserving verification accuracy.
2Reliability
If multiple precharging and sensing steps are performed, then verification reliability is improved, but device complexity increases
Solution Approach 1:
The sensing node serves multiple functions by operating at different potentials for different verification stages. Instead of requiring separate sensing nodes for each verify operation, a single sensing node is used universally for both first and second verify operations at different voltages, simplifying the device structure while maintaining verification reliability.
Solution Approach 2:
The potential of the sensing node is changed from a first potential to a second potential to accommodate different verification requirements. By dynamically adjusting the voltage parameter of the sensing node rather than using fixed voltage levels, the system achieves reliable verification across multiple states without increasing operational complexity.
Data Source
AI summary
The present application discloses example operation methods of a memory, memories, memory systems and electronic systems. An example memory includes a page buffer, and the page buffer includes a first sensing circuit coupled to the sensing node and a dynamic storage circuit coupled to the first sensing circuit. An example memory cell included in the memory is configured to store one of programmed states. An example operation method includes: storing first verification information into the first sensing circuit based on a first potential of the sensing node; transmitting initial verification information in the dynamic storage circuit to the sensing node; transmitting the first verification information from the first sensing circuit to the dynamic storage circuit; performing a clearing operation on the first sensing circuit; and storing second verification information or the initial verification information into the first sensing circuit based on a second potential of the sensing node.