NAND Page Buffer Circuit Sharing for Higher Bit Line Density
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Solution Overview
Problem
The limited number of page buffers in NAND flash memory systems restricts storage capacity and write speed due to their large circuit size, which occupies a significant portion of the die area and limits the number of bit lines and concurrency of programming processes.
Innovation Solution
A new circuit structure for the page buffer is introduced, allowing each page buffer to have two bit line connection points with independent precharge circuits, sharing a part of the circuit structure during program and read operations, reducing the overall size of the page buffer while maintaining the number of bit lines unchanged, and increasing the number of bit lines without altering the die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of page buffers is increased to improve storage capacity and write speed, then the die area occupied by page buffers increases, which worsens the available area for bit lines and memory cells
Solution Approach 1:
The patent merges multiple bit line connection functions into a single page buffer by providing multiple bit line connection points (first bit line connection point and second bit line connection point) within one page buffer structure. This allows one page buffer to serve multiple bit lines simultaneously, reducing the total number of page buffers needed and thereby reducing the die area occupied by page buffers while maintaining or improving write speed through concurrent programming operations.
Solution Approach 2:
The page buffer is designed with multi-functionality by enabling a single page buffer to connect to and operate on multiple bit lines through multiple bit line connection points. This universal design allows the page buffer to perform programming operations on different bit lines concurrently, improving overall system productivity without requiring proportional increases in page buffer quantity and die area.
2Area of stationary object
If the circuit size of each page buffer is reduced to free up die area, then the functionality and performance of the page buffer may be compromised
Solution Approach 1:
The patent combines multiple bit line interface functions into a single page buffer structure with multiple bit line connection points. This merging approach allows the page buffer to maintain comprehensive functionality for handling multiple bit lines while using a more area-efficient design compared to having separate page buffers for each bit line, thereby freeing up die area while preserving storage capacity.
Solution Approach 2:
The page buffer structure is segmented into distinct functional components including first and second bit line connection points, precharge circuits, and switching components. This segmentation allows for optimized area utilization by arranging these components efficiently and sharing common resources among multiple bit line interfaces, reducing overall circuit size while maintaining full functionality.
3Quantity of substance
If more bit lines are added to increase storage capacity, then the die area available for page buffers and control circuits is reduced
Solution Approach 1:
The patent implements a universal page buffer design that can interface with multiple bit lines through multiple bit line connection points. This allows the system to support a larger number of bit lines (and thus increased storage capacity) without requiring a proportional increase in page buffer quantity, as each page buffer can serve multiple bit lines. This multi-functionality enables more bit lines to be accommodated within the same die area.
Solution Approach 2:
The patent merges multiple bit line connection capabilities into single page buffer structures, reducing the total number of page buffers required for a given number of bit lines. This merging strategy frees up die area that would otherwise be occupied by additional page buffers, allowing more space to be allocated to memory cells and control circuits while supporting an increased number of bit lines for enhanced storage capacity.
Data Source
AI summary
This application provides a memory including a peripheral circuit and a memory cell array. The peripheral circuit includes a page buffer including a first bit line connection point, a second bit line connection point, a first switching component and a second switching component. The first bit line connection point and the second bit line connection point are connected to a power terminal via independent precharge circuits respectively, and the first bit line connection point and the second bit line connection point are connected to a latch in the page buffer respectively; the precharge circuit is a circuit for precharging the bit lines by the page buffer; the first switching component connects the first bit line connection point and the second bit line connection point; and the second switching component is located on the precharge circuit corresponding to the second bit line connection point.