NAND Memory Page Coding Rate Adaptation for Bit Error Mitigation
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Solution Overview
Problem
In non-volatile semiconductor memories like NAND flash, bit errors increase due to repeated write and erase cycles, leading to memory cell exhaustion and interference with adjacent cells, which existing error mitigation techniques fail to adequately address.
Innovation Solution
A memory system that employs error mitigation coding with adaptive coding rates based on page-specific error characteristics, using error mitigation encoders and decoders to adjust coding rates for each page, combined with error correction coding to improve reliability and reduce bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error mitigation coding with fixed coding rate is used, then error correction capability is improved, but adaptability to page-specific error characteristics deteriorates
Solution Approach 1:
The patent applies dynamics by making the coding rate adjustable and adaptable based on page-specific error characteristics. The error mitigation encoder dynamically selects coding rates from multiple available rates according to the actual error conditions of each page, transforming a static fixed-rate system into a dynamic adaptive system that optimizes error correction for varying error patterns across different pages.
Solution Approach 2:
The patent changes the parameter of coding rate from a fixed value to a variable that can be selected from multiple rates. By introducing multiple coding rate options and selecting appropriate rates based on page-specific error characteristics, the system adjusts the error mitigation parameter to match actual error conditions, resolving the contradiction between reliable error correction and adaptability.
2Adaptability or versatility
If adaptive coding rates for each page are used, then adaptability to error characteristics is improved, but device complexity increases
Solution Approach 1:
The patent segments the error mitigation process by page, allowing each page to have its own error characteristics analysis and coding rate selection. This segmentation enables targeted error correction strategies for different pages without requiring complete system redesign, managing complexity through modular page-level processing while maintaining high adaptability.
Solution Approach 2:
The patent implements feedback mechanisms where error characteristics are analyzed from read data, and this information feeds back into the coding rate selection process. The error mitigation decoder provides feedback about error patterns to the encoder, enabling adaptive coding rate adjustment that improves error correction while managing complexity through intelligent feedback-driven decision making.
3Reliability
If multiple coding rates are supported, then error mitigation performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent supports multiple coding rates but implements them selectively based on actual error conditions rather than always using the most complex rate. By applying partial action - using higher coding rates only when error characteristics demand them - the system achieves improved error mitigation performance while avoiding unnecessary manufacturing precision requirements that would arise from always implementing the full capability set.
Data Source
AI summary
According to one embodiment, a memory system includes an error mitigation encoder that executes error mitigation coding on write data to be stored in a processing target page of a non-volatile memory, a memory interface that writes the write data which has undergone the error mitigation coding in the processing target page of the non-volatile memory and reads the write data which has undergone the error mitigation coding from the processing target page as read data, an error mitigation decoder that performs error mitigation decoding on the read data read from the processing target page of the non-volatile memory, and an error mitigation coding rate deciding unit that decides an error mitigation coding rate of the error mitigation encoder and the error mitigation decoder on the basis of at least one of information indicating the processing target page and information indicating a device characteristic of the processing target page.