NAND Memory Page Control With Data-State Conversion

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Solution Overview

Problem

Existing NAND flash memory technologies face challenges in efficiently storing and retrieving data, particularly in managing multiple data pages and ensuring reliable data storage and retrieval operations.

Innovation Solution

The semiconductor memory device incorporates a memory cell array with two or more memory cells, a control circuit that controls write and read operations, and a logic circuit to manage data conversion, enabling efficient storage and retrieval of data by setting cell states and converting read data based on second data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional NAND flash memory is used for data storage, then nonvolatile data storage is achieved, but data management efficiency and reliability are insufficient

Engineering Contradiction:
Improvedata storage reliabilityVSAvoiddata management efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides data management into multiple independent pages within the memory cell array, allowing parallel processing and independent management of different data sets. This segmentation enables efficient handling of multiple data pages simultaneously while maintaining reliable storage through structured page-level organization and control

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control circuit acts as an intermediary between the memory cell array and external systems, managing write and read operations across multiple pages. It coordinates data flow, handles page selection, and ensures reliable data transfer while improving overall management efficiency through centralized control

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If multiple data pages are stored in the memory cell array, then data storage capacity is increased, but data conversion and retrieval complexity increases

Engineering Contradiction:
Improvedata storage capacityVSAvoiddata conversion complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The control circuit is designed with multi-functional capabilities to handle write operations, read operations, and data conversions across all pages uniformly. This universal design allows the same circuitry to manage multiple data pages with different formats and requirements, reducing overall system complexity while maintaining high storage capacity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs data conversion mechanisms that change data parameters (such as formatting, encoding, or organization structure) when writing to or reading from different pages. By dynamically adjusting data parameters based on page requirements, the system can efficiently manage multiple pages without proportionally increasing conversion complexity

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12542180B2Semiconductor memory device
Publication Date: 2026.02.03 KIOXIA CORP
  • US12542180B2 patent drawing
  • US12542180B2 patent drawing
  • US12542180B2 patent drawing

AI summary

According to one embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes two or more memory cells. The control circuit is configured to control a write operation of writing first data to the two or more memory cells and a read operation of reading the first data from the two or more memory cells. The control circuit sets cell states of the two or more memory cells based on second data included in the first data in the write operation. The control circuit converts read data into the first data based on the second data included in data read from the two or more memory cells in the read operation.