NAND Flash Two-Stage Page Writes for Threshold Stability
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Solution Overview
Problem
NAND flash memory systems face challenges in maintaining data reliability due to initial drop phenomena and parasitic capacitance effects, which cause threshold voltage deviations and reliability issues during write operations.
Innovation Solution
The implementation of a 1-2-4-8 code data assignment and divisional write operations, where 4-page data is written in two separate write operations, with the first write operation focusing on lower and middle bits and the second on upper bits, while also using internal data load (IDL) to restore data and reduce the impact of initial drop and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 4-page data is written in a single write operation, then write speed is improved, but threshold voltage deviation and data reliability deteriorate due to initial drop and parasitic capacitance effects
Solution Approach 1:
The patent divides a 4-page data write operation into two separate write operations: a first write operation for lower and middle bits, and a second write operation for upper bits. This segmentation reduces the number of memory cells simultaneously affected by write disturbances, thereby minimizing threshold voltage deviation and initial drop effects while maintaining acceptable write speed through efficient bit grouping.
Solution Approach 2:
The patent applies different write strategies to different bit groups (lower/middle bits vs. upper bits) based on their susceptibility to write disturbances. By identifying and treating critical bit groups with enhanced protection measures during specific write operations, the system optimizes reliability for each bit group according to its local characteristics without sacrificing overall write performance.
2Reliability
If RAM capacity in controller is increased to buffer data for divisional writes, then data reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines the buffer function with existing controller structures, integrating data buffering capabilities into the control logic rather than adding separate dedicated buffer memory. This merging approach allows the controller to handle divisional write operations using existing resources, improving reliability through staged writing without proportionally increasing device complexity or cost.
Solution Approach 2:
The controller utilizes its own internal resources and existing data paths to manage the divisional write process, rather than requiring external buffering infrastructure. By self-managing the data staging and retrieval for separate write operations, the controller achieves improved reliability while minimizing additional complexity through efficient use of built-in capabilities.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.