NAND Parity Management via Non-Volatile Swap Block
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Solution Overview
Problem
Mobile devices often lack sufficient RAM to maintain parity information for NAND memory devices, leading to potential data loss during programming, as they do not have enough resources to handle the aggregate parity information for open data stripes.
Innovation Solution
A non-volatile swap block is used in conjunction with a small RAM buffer to manage parity information, allowing parity data to be stored and updated in a dedicated area of the NAND memory until programming is complete, enabling recovery from data corruption and balancing performance with minimal RAM utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a small RAM buffer is used to manage parity information, then RAM utilization is minimized, but the ability to maintain parity information for all open data stripes is compromised
Solution Approach 1:
The patent divides the parity information management into segments: active parity information kept in the small RAM buffer and inactive parity information stored in the non-volatile swap block. This segmentation allows the system to maintain data integrity for currently programmed data stripes while minimizing RAM usage by offloading previously completed parity information to non-volatile storage.
Solution Approach 2:
The patent introduces a temporal dimension to parity information management by implementing a swap block mechanism that preserves parity information across programming operations. Instead of requiring all parity information to reside simultaneously in RAM, the system uses non-volatile storage to maintain parity data across different time periods and programming cycles, effectively adding a time-based dimension to the storage architecture.
2Reliability
If parity information is stored in non-volatile memory, then data recovery capability is improved, but access speed deteriorates
Solution Approach 1:
The patent applies local quality by maintaining different storage characteristics for different types of parity information. Active parity information that needs frequent access during programming operations is kept in the fast RAM buffer, while inactive parity information that is needed less frequently is stored in the non-volatile swap block. This creates a hierarchical storage system with varying access speeds matched to the specific needs of different data sets.
Solution Approach 2:
The system performs preliminary actions by pre-calculating and storing parity information in the swap block before it is potentially needed for recovery operations. This allows the parity information to be prepared in advance in non-volatile storage, so when data corruption occurs, the recovery process can quickly retrieve the pre-computed parity information without requiring time-consuming calculations at the moment of failure.
Data Source
AI summary
Disclosed in some examples are techniques for handling parity data of a non-volatile memory device with limited cache memory. In certain examples, user data can be programmed into the non-volatile memory of the non-volatile memory device in data stripes, and parity information can be calculated for each individual data stripe within a limited capacity cache of the non-volatile memory device. The individual parity information can be swapped between a swap block of the non-volatile memory and the limited capacity cache as additional data stripes are programmed.