NAND Memory Parity Recovery for Adjacent Word Line Write Failures
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Solution Overview
Problem
As device pitch of wirings in nonvolatile semiconductor memory decreases, maintaining reliability becomes increasingly difficult due to issues like data loss and failure in writing data, particularly due to short circuits between adjacent word lines.
Innovation Solution
A semiconductor memory device with a controller that maintains parity data and uses this data to restore information from adjacent memory cells when a failure is detected, employing a reproduction information control unit to perform XOR operations across multiple memory channels to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device pitch of wirings is decreased to increase storage capacity, then storage density is improved, but reliability deteriorates due to short circuits between adjacent word lines
Solution Approach 1:
The system performs preliminary actions by writing parity data to memory cells adjacent to the target memory cells before the actual data write operation. This preliminary placement of parity data enables subsequent data restoration if a short circuit occurs during the write operation, thus maintaining reliability while using smaller device pitch.
Solution Approach 2:
The invention converts the harmful effect of short circuits between adjacent word lines into a beneficial restoration mechanism. When a short circuit is detected, the system uses the pre-positioned parity data to restore the lost data, thereby transforming the reliability problem caused by decreased device pitch into a solvable error condition.
2Reliability
If parity data is maintained and XOR operations are performed across multiple memory channels to restore data, then reliability is improved, but device complexity increases
Solution Approach 1:
The system segments the data protection mechanism into distinct components: parity data storage in adjacent memory cells, detection logic for short circuits, and restoration logic using XOR operations. This segmentation allows the complex error restoration function to be implemented as modular additions to the existing memory controller architecture.
Solution Approach 2:
The parity data acts as an intermediary element between the original data and the restoration process. By maintaining parity data in adjacent memory cells and using XOR operations as the intermediary calculation method, the system can restore lost data without requiring complex direct recovery mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the semiconductor memory device by effectively reproducing data lost due to short circuits and failures, maintaining data integrity across memory channels.
Implementation Method 1
perform XOR operations across multiple memory channels to ensure data integrity
Data Source
AI summary
A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A method of operating the storage device includes maintaining parity data for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restoring the data written to the first memory cells using the parity data.