NAND Partial Checksum Circuit for Low-Gate RBER Estimation
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Solution Overview
Problem
NAND flash memory devices face challenges with reduced lifespan and decreased data reliability due to fabrication process limitations, necessitating improved error correction methods for data integrity.
Innovation Solution
Implementing a partial checksum calculation using a sub-matrix with flexible media coverage within the memory device, specifically through a gate-count efficient syndrome calculator module, to estimate the raw bit error rate (RBER) without the need for transferring data to a system-on-a-chip (SOC).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full checksum calculations are performed using the complete parity check matrix, then accurate bit error rate estimation is achieved, but design complexity and gate count increase significantly
Solution Approach 1:
The parity check matrix H is divided into multiple sub-matrices, where only a selected subset of rows (forming sub-matrix H1) is used for checksum calculation. This segmentation allows the system to perform error rate estimation using a reduced matrix portion, thereby reducing gate count and design complexity while maintaining sufficient accuracy for error detection purposes.
Solution Approach 2:
Instead of performing complete checksum calculations using all rows of the parity check matrix, the invention applies partial action by using only a subset of rows (m1 <= m) to calculate the checksum. This partial calculation approach reduces the computational burden and hardware requirements while still providing effective bit error rate estimation for NAND flash memory error correction.
2Reliability
If full checksum calculations are performed using the complete parity check matrix, then accurate error detection is achieved, but memory requirements and power consumption increase
Solution Approach 1:
The parity check matrix is segmented into sub-matrices, and only the necessary subset of rows is stored and processed for checksum calculation. This reduces the memory storage requirements within the NAND device while maintaining the ability to detect errors effectively through the reduced matrix operations.
3Reliability
If complete parity check matrix operations are performed, then comprehensive error correction is achieved, but data transfer to system-on-a-chip increases
Solution Approach 1:
The invention performs partial checksum calculations using a subset of the parity check matrix rows directly within the NAND device. This allows error detection and data integrity verification to be performed locally without transferring all data to the system-on-a-chip, thereby improving productivity by reducing unnecessary data transfer while maintaining comprehensive error correction capabilities through the partial matrix operations.
Data Source
AI summary
A memory device and method for a partial checksum calculation using a sub-matrix with flexible media coverage inside of a memory device (i.e., NAND) of a memory system. The memory device includes: a plurality of memory cells; a control circuit configured to read a codeword sequence from the plurality of memory cells, and determine a sub-matrix including multiple non-zero circulants selected from particular matrix rows of a parity check matrix used in a controller of the memory system, the multiple non-zero circulants including non-zero row circulants for each matrix row; and a partial checksum calculator configured to perform a partial checksum calculation on a syndrome sequence based on the codeword sequence and the sub-matrix.