3D NAND Memory Pillar Recess Layout for Back Tunneling Control
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Solution Overview
Problem
The existing semiconductor storage devices, such as NAND flash memories, face reliability issues due to the back tunneling phenomenon during erasing operations, which can lead to threshold voltage shifts and malfunctions, particularly in the uppermost wiring layers where electric field concentrations occur.
Innovation Solution
The semiconductor storage device is designed with a specific configuration where the lower memory pillar does not have protrusion parts on the uppermost and second-to-uppermost wiring layers, while other layers have protrusion parts, creating a recess region that reduces the step width between insulating and wiring layers, thereby minimizing the back tunneling phenomenon and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If protrusion parts are provided on all wiring layers to increase storage capacity, then the storage capacity is improved, but the back tunneling phenomenon occurs during erasing operations causing reliability degradation
Solution Approach 1:
The patent applies local quality by providing protrusion parts on memory pillars only in specific wiring layers (first through third wiring layers from the lower end) while intentionally omitting them from the uppermost and second-to-uppermost wiring layers. This creates a localized structural variation that reduces the step width between insulating and wiring layers at critical positions, thereby suppressing the back tunneling phenomenon during erasing operations while maintaining storage capacity in other layers.
2Reliability
If the step width between insulating and wiring layers is reduced to prevent back tunneling, then reliability is improved, but the structural complexity increases
Solution Approach 1:
The patent segments the memory pillar structure by dividing the wiring layers into different groups: lower wiring layers (first through third from lower end) that include protrusion parts, and upper wiring layers (uppermost and second-to-uppermost) that exclude them. This segmentation allows the structure to optimize for different functions at different heights - maintaining storage capacity at lower levels while preventing back tunneling at upper levels where electric field concentration occurs during erasing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the likelihood of back tunneling, improving the overall reliability of the semiconductor storage device by maintaining consistent electric field strengths across the memory pillars and preventing threshold voltage shifts during erasing operations.
Implementation Method 1
reliability issues due to the back tunneling phenomenon during erasing operations, which can lead to threshold voltage shifts and malfunctions
Data Source
AI summary
A semiconductor storage device includes a first wiring layer, a first insulating layer on the first wiring layer, a second wiring layer on the first insulating layer, a second insulating layer on the second wiring layer, a third wiring layer on the second insulating layer, and a first pillar that passes through the first, second, and third wiring layers and the first and second insulating layers along a first direction and includes a first semiconductor layer. A first distance between side surfaces of the first wiring layer and the first insulating layer facing the first pillar is greater than a second distance between side surfaces of the second wiring layer and the second insulating layer facing the first pillar and a third distance between the side surfaces of the second insulating layer and the third wiring layer facing the first pillar.