3D NAND Memory Pillar Isolation Structure for Reliable Insulation
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Solution Overview
Problem
Existing three-dimensional NAND flash memory devices face challenges in maintaining reliable connections and insulation between memory pillars and conductive layers, leading to potential defects and reduced device reliability.
Innovation Solution
The implementation of a stacked body structure with insulation layers and isolation regions to isolate memory pillars and conductive layers, using silicon nitride and oxide layers to control thickness and prevent etching errors, and to terminate dangling bonds in memory transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory pillars are three-dimensionally arranged in NAND flash memory, then storage density is improved, but connection reliability and insulation between memory pillars and conductive layers deteriorate
Solution Approach 1:
The patent divides the memory structure into distinct segments with separate functions: charge trapping layers for data storage, tunnel insulation layers for electrical isolation, block insulation layers for structural separation, and interlayer insulation layers for conductive layer isolation. This segmentation allows each layer to optimize its specific function while maintaining overall reliability in the three-dimensional arrangement.
Solution Approach 2:
The patent introduces multiple intermediary insulation layers (tunnel insulation layers, block insulation layers, interlayer insulation layers) that act as mediators between memory pillars and conductive layers. These intermediary layers prevent direct contact and potential short circuits, ensuring reliable insulation while maintaining the high-density three-dimensional structure.
2Reliability
If insulation layers are added to isolate memory pillars and conductive layers, then connection reliability is improved, but device complexity increases
Solution Approach 1:
The patent designs insulation layers that serve multiple functions simultaneously: tunnel insulation layers provide both electrical isolation and structural support, block insulation layers serve as both separators and etch stoppers, and interlayer insulation layers provide both insulation and planarization. This multi-functionality reduces the need for additional dedicated layers, thereby limiting complexity increase.
Solution Approach 2:
The patent combines multiple insulation functions into integrated layer structures where tunnel insulation layers, block insulation layers, and interlayer insulation layers work together as a unified insulation system. This merging approach streamlines the overall structure and simplifies manufacturing processes compared to implementing separate dedicated layers for each insulation function.
3Manufacturing precision
If multiple insulation layers are used to control thickness, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent incorporates etch stopper layers within the insulation layer structure that are deposited beforehand to define precise thickness boundaries. These preliminary etch stoppers enable subsequent etching processes to achieve accurate thickness control for tunnel insulation layers, block insulation layers, and interlayer insulation layers without requiring complex real-time monitoring.
Solution Approach 2:
The patent replaces complex mechanical thickness measurement and control systems with material-based etch stopper layers that inherently define thickness boundaries through their distinct etching characteristics. This substitution simplifies the manufacturing process by using material properties rather than complex mechanical control systems to achieve precise thickness control.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.