3D NAND Pillar Isolation Trenches for Higher Cell Density

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Solution Overview

Problem

The challenge in microelectronic device fabrication, particularly in 3D NAND memory devices, is to increase the number of operational features within a given footprint without negatively impacting device design and operation.

Innovation Solution

The formation of isolation trenches in the upper portions of pillars in microelectronic devices, which reduces the horizontal cross-sectional area of these pillars, allowing them to function as select gate devices while eliminating the need for dummy pillars that occupy valuable space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If dummy pillars are used to maintain device structure, then structural integrity is improved, but device footprint area increases

Engineering Contradiction:

Improvestructural integrityVSAvoiddevice footprint area

Core Design Contradiction:

Stability of the object's compositionVSArea of stationary object

Solution Approach 1:

The patent removes dummy pillars from the device structure, extracting the non-functional elements that were occupying valuable footprint area. The isolation trenches are formed to eliminate the need for dummy pillars while maintaining structural integrity through the tiered stack design.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a two-dimensional planar arrangement to a three-dimensional tiered stack structure. By stacking multiple tiers vertically with alternating conductive and insulative structures, the device achieves higher integration density without increasing footprint area, eliminating the need for dummy pillars.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If pillar cross-sectional area is reduced in upper portions, then packing density is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvepacking densityVSAvoidpillar formation precision

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent divides the pillar structure into multiple tiers with alternating conductive and insulative structures. Each tier is formed as a separate segment, allowing independent optimization of cross-sectional areas at different heights. The isolation trenches further segment the upper portions, enabling reduced cross-sectional area without compromising overall structural integrity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different cross-sectional areas to different portions of the pillars. The upper portions have reduced cross-sectional area to increase packing density, while the lower portions maintain larger areas for structural support. This local differentiation of geometric properties optimizes both density and manufacturability.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250301648A1Microelectronic devices including pillars with upper portions having perimeters interrputed by elongate isolation structures

Publication Date: 2025.09.25 LODESTAR LICENSING GROUP LLC

AI summary

Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.