3D NAND Memory Pillar Layout for Isolation and Density
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Solution Overview
Problem
Existing NAND-type flash memory technologies face challenges in optimizing the structure and manufacturing process to enhance data storage capacity and reliability while maintaining efficiency and cost-effectiveness.
Innovation Solution
The semiconductor memory device employs a novel configuration with stacked conductive layers, insulating members, and pillars, featuring specific pillar distances and insulating layer thicknesses to optimize data storage capacity and reliability, utilizing a manufacturing process that includes the formation of memory pillars and trenches to enhance electrical isolation and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked conductive layers and pillars is increased to enhance data storage capacity, then the storage density improves, but the manufacturing precision and electrical isolation become more difficult to maintain
Solution Approach 1:
The memory device is divided into multiple independent string units, each containing memory cells formed by intersections of word lines and bit lines. This segmentation allows the storage capacity to be increased by adding more string units without proportionally increasing the complexity of each individual cell structure, thereby maintaining manufacturing precision while scaling capacity.
Solution Approach 2:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional stacked conductive layers. Multiple conductive layers are stacked vertically to form multiple bit line levels, enabling increased storage capacity in the vertical dimension while maintaining consistent pillar distances and electrical isolation characteristics in each layer.
2Volume of moving object
If the conductive layers are stacked closely to increase storage density, then the volume efficiency improves, but the electrical isolation between layers becomes more challenging
Solution Approach 1:
Insulating layers are introduced as intermediary structures between adjacent conductive layers. These insulating layers provide electrical isolation while allowing the conductive layers to be stacked closely together, thereby maintaining high storage density without compromising electrical isolation reliability between neighboring bit lines and word lines.
3Quantity of substance
If the pillar dimensions are reduced to increase the number of memory cells per unit area, then the storage capacity increases, but the manufacturing precision requirements become more stringent
Solution Approach 1:
Pillar structures are formed preliminarily before the formation of conductive layers and insulating layers. By establishing the pillar positions and dimensions early in the manufacturing process, subsequent layers can be deposited and patterned with reference to these pre-formed pillars, reducing the cumulative precision requirements and enabling higher cell density without proportionally increasing manufacturing difficulty.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes first to ninth conductive layers, first and second insulating members, and first to fourth pillars. A distance between the first and second pillars in a cross section including the second conductive layer and the sixth conductive layer is smaller than a distance between the first and second pillars in a cross section including the third conductive layer and the seventh conductive layer. A distance between the third and fourth pillars in a cross section including the fourth conductive layer and the eighth conductive layer is greater than a distance between the third and fourth pillars in a cross section including the fifth conductive layer and the ninth conductive layer.