NAND Memory Plane Biasing for Uniform Program and Erase
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Solution Overview
Problem
Existing NAND memory devices face challenges in achieving uniformity in programming and erasing across multiple planes within a chip due to variations in distance from the voltage pump, leading to inconsistent performance.
Innovation Solution
The method involves adjusting voltage parameters such as ramp rate and bias voltage based on the distance between memory planes and voltage pumps (VERA and VPGM) to ensure consistent programming and erasing across all planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single voltage pump is used to serve multiple planes, then device complexity is reduced, but programming and erasing uniformity deteriorates due to distance variations
Solution Approach 1:
The patent applies local quality by providing each plane with its own dedicated voltage pump (VERA pump for erase, VPGM pump for program) instead of sharing a single pump. This ensures that each plane receives consistent voltage levels regardless of its position on the chip, thereby achieving uniform programming and erasing characteristics across all planes while maintaining relatively simple device architecture.
2Manufacturing precision
If voltage parameters are adjusted based on plane distance, then programming and erasing consistency is improved, but control complexity increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring each plane with dedicated voltage pumps that are inherently positioned to provide optimal voltage levels to their respective planes. This eliminates the need for dynamic voltage parameter adjustments based on distance, as the voltage consistency is achieved through the initial architectural design rather than complex control mechanisms.
3Manufacturing precision
If multiple voltage pumps are allocated to different planes, then programming and erasing uniformity is improved, but device complexity and area increase
Solution Approach 1:
The patent applies segmentation by dividing the voltage supply function into separate dedicated pumps for each plane (VERA pumps for erase operations, VPGM pumps for program operations). This segmentation ensures that each plane has its own voltage source optimized for its specific location and requirements, achieving uniform performance across the chip while managing area through functional specialization rather than redundant components.
Data Source
AI summary
The memory device includes a chip with at least one voltage pump and a plurality of planes. The planes have arrays of memory cells that can be programmed and erased. At least some of the planes are at different distances from the at least one voltage pump. The memory device further includes control circuitry that is configured to program and erase the memory cells. The control circuitry is further configured to supply at least one voltage to a selected plane of the plurality of planes during a programming operation or an erase pulse and adjust the at least one voltage that is supplied to the selected plane by a parameter that is determined based on a distance between the selected plane and the at least one voltage pump.