NAND Memory Plane Compression for Parallel Soft-Decision Output
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Solution Overview
Problem
NAND flash memory devices face challenges in accurate data reading over time due to voltage variations, which traditional hard decision technology struggles to address effectively, leading to performance issues and reduced lifespan.
Innovation Solution
Implementing a nonvolatile memory device with parallel data compression and output capabilities, utilizing page buffer circuits, compression engines, and local clock controllers to process soft decision data, allowing for parallel encoding and output operations, thereby enhancing data handling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional hard decision technology is used for data reading, then the device structure remains simple, but data reading accuracy deteriorates over time due to voltage variations
Solution Approach 1:
The patent divides the data reading process into two independent paths: hard decision path and soft decision path. The hard decision path maintains simple structure for basic reading, while the soft decision path provides enhanced accuracy through additional voltage analysis. This segmentation allows the system to improve measurement precision without requiring the entire device structure to become complex.
Solution Approach 2:
The memory device is designed to support both hard decision and soft decision reading modes through a unified architecture. The same memory array and basic reading circuitry serve dual purposes, while optional soft decision components are added only when needed. This multi-functionality allows the device to maintain simplicity for basic operations while providing enhanced accuracy capabilities when required.
2Measurement precision
If soft decision technology is implemented to improve data reading accuracy, then data reading accuracy improves, but processing time increases due to additional voltage analysis
Solution Approach 1:
The patent performs preliminary hard decision reading first to quickly determine the most likely data value. Only when the hard decision result is uncertain or error correction is needed does the system proceed to the more time-consuming soft decision voltage analysis. This preliminary action approach minimizes the average processing time while maintaining high accuracy for difficult cases.
Solution Approach 2:
The system applies soft decision voltage analysis selectively rather than to all data reads. For clear, unambiguous memory cell states, only the necessary hard decision is performed. For borderline cases where accuracy is critical, the full soft decision analysis is applied. This partial application of the more time-consuming process optimizes the balance between speed and accuracy.
3Productivity
If data is compressed and output in parallel to reduce timing intervals, then channel occupancy is optimized, but device complexity increases due to additional compression engines and control circuits
Solution Approach 1:
The patent segments the data output function into separate compression engines for each memory plane, with each engine handling compression independently. This modular segmentation allows parallel processing of data from multiple planes simultaneously, optimizing channel occupancy. The segmented architecture also contains complexity within discrete units rather than requiring a monolithic complex system.
Solution Approach 2:
The patent introduces compression engines as intermediary components between the memory array and the external interface. These intermediaries perform data compression and formatting, allowing the memory device to output data more efficiently and occupy the communication channel more effectively. The intermediary layer adds functionality without requiring fundamental changes to the core memory structure.
4Productivity
If parallel compression and output operations are performed, then data handling efficiency improves, but control complexity increases due to multiple clock controllers and coordination requirements
Solution Approach 1:
The patent divides the control function into multiple independent local clock controllers, each dedicated to controlling a specific compression engine. This segmentation of control authority allows each controller to manage its associated compression engine independently without interference from other controllers, simplifying the control logic within each unit while enabling parallel operation across multiple units.
Solution Approach 2:
Each local clock controller is designed to autonomously generate and manage its own clock signals for its associated compression engine without requiring centralized coordination. This self-service approach to clock management allows parallel compression operations to proceed independently, improving data handling efficiency while avoiding the complexity of synchronized control across multiple engines.
Data Source
AI summary
An example nonvolatile memory device includes page buffer circuits, compression engines, local clock controllers, a data input/output (I/O) circuit, and a control circuit. Each compression engine is connected with a respective page buffer circuit through respective local data lines. The control circuit controls each compression engine to perform an encoding operation based on receiving soft decision data from target cache latches corresponding to an output address, based on compressing the received soft decision data, and based on overwriting the compressed soft decision data in the target cache latches based on an input address. The control circuit controls one or more page buffer circuits among the plurality of page buffer circuits to perform an output operation based on outputting the compressed soft decision data through the data I/O circuit, the output operation performed in parallel with the encoding operation or independently from the encoding operation.