3D NAND Conductive Plug Tapering to Reduce Capacitive Coupling

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Solution Overview

Problem

In microelectronic device fabrication, particularly for 3D NAND Flash memory devices, reducing feature spacing leads to undesirable electrical coupling effects, such as capacitive coupling, which increases programming time and affects high-speed memory performance.

Innovation Solution

The method involves forming microelectronic devices with vertically alternating conductive and insulative structures, using specific geometric configurations for conductive plug structures to reduce capacitive coupling, including tapered profiles and precise alignment of conductive and insulative materials to minimize electrical interference between neighboring features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If feature spacing is reduced to increase memory density, then packaging density increases, but capacitive coupling between conductive structures increases causing programming time margin loss

Engineering Contradiction:

Improvememory densityVSAvoidcapacitive coupling

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

An insulative structure is introduced as an intermediary between adjacent conductive plug structures. This insulative structure acts as a mediator that reduces direct capacitive coupling between the conductive structures while allowing them to maintain close spacing for high density. The insulative material fills the space between conductive plugs and extends vertically along their sides, creating electrical isolation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulative structure is formed in advance between conductive plug structures before final device operation. By pre-establishing this insulative barrier, the harmful capacitive coupling effect is prevented from occurring during device operation. The insulative material is deposited and patterned to create preliminary separation between conductive elements.

Inventive Principle:

Principle #9Preliminary anti-action

2Area of stationary object

If conductive structures are closely arranged to increase integration, then area utilization improves, but electrical interference and capacitive coupling increase

Engineering Contradiction:

Improvearea utilizationVSAvoidelectrical interference

Core Design Contradiction:

Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The insulative structure serves as a mediator positioned between closely spaced conductive plug structures. It allows the conductive structures to maintain close horizontal spacing for area efficiency while providing vertical and lateral electrical isolation. The insulative material creates an electromagnetic barrier that reduces interference between adjacent conductive elements.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulative structure provides localized electrical isolation specifically where conductive plug structures are in close proximity. Rather than uniformly increasing spacing between all conductive elements, the insulative material is strategically placed only between adjacent conductive plugs where capacitive coupling is most problematic, allowing other areas to maintain optimal spacing for performance.

Inventive Principle:

Principle #3Local quality

3Productivity

If vertical memory array area is reduced to increase feature density, then manufacturing scalability improves, but capacitive coupling effects become more pronounced

Engineering Contradiction:

Improvemanufacturing scalabilityVSAvoidcapacitive coupling effects

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The solution moves from a two-dimensional planar separation approach to a three-dimensional insulative structure. Instead of increasing horizontal spacing between conductive plugs, the insulative material extends vertically along the sides of conductive plugs and fills the space between them in the vertical dimension. This 3D configuration reduces capacitive coupling while maintaining the compact 2D footprint required for high-density manufacturing.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The insulative structure acts as a mediator that enables further scaling of vertical memory arrays by reducing capacitive coupling effects that become more pronounced at higher densities. It allows manufacturers to continue reducing vertical array area and increasing feature density without being limited by capacitive coupling-induced programming time penalties.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11901292B2Microelectronic devices, memory devices, and electronic systems

Publication Date: 2024.02.13 MICRON TECHNOLOGY INC

AI summary

A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises an upper portion having a first width, and a lower portion vertically interposed between the upper portion and the contact structures. The lower portion has a tapered profile defining additional widths varying from a second width less than the first width at an uppermost boundary of the lower portion to a third width less than the second width at a lowermost boundary of the lower portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.