NAND Memory POR State Management to Reduce Toggle Current
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Solution Overview
Problem
The challenge of high power consumption during Power On Reset (POR) operations in NAND type memory devices due to the identification and redistribution of failed memory cells, which affects the efficiency and performance of the memory device.
Innovation Solution
Implementing a memory device with a memory cell array comprising both main and redundant memory areas, where the peripheral circuit sets initial state information to normal for all main areas and modifies based on a match result during POR, reducing the number of state information modifications and toggle current applications to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the peripheral circuit identifies and redistributes failed memory cells during Power On Reset operations, then the reliability of the memory device is improved, but the power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-setting all main memory area state information to normal state before Power On Reset operations. This eliminates the need to identify and redistribute failed cells during POR, as the system proactively prepares all areas as potentially functional. The redundant memory area is pre-configured as backup, ready to assume functionality if needed, thus avoiding power-consuming identification and redistribution processes during actual POR operations.
2Reliability
If the peripheral circuit modifies state information for all main memory areas during POR, then the reliability is improved, but the number of operations and time consumption increase
Solution Approach 1:
The patent extracts the identification and redistribution operations from the Power On Reset process. Instead of performing comprehensive failed cell identification and state information modification for all main memory areas during POR, the system separates these functions: the state information is pre-set to normal, and actual identification/redistribution only occurs when genuinely needed (when redundant area needs to assume functionality). This extraction eliminates unnecessary operations during routine POR, reducing time consumption while maintaining reliability.
3Reliability
If the peripheral circuit applies toggle current multiple times to modify state information, then the reliability is improved, but the power consumption and operational complexity increase
Solution Approach 1:
The patent applies preliminary action by pre-configuring the redundant memory area as a ready backup with appropriate state information. This preliminary setup eliminates the need for multiple toggle current applications during Power On Reset, as the system doesn't need to perform repeated state modifications to ensure reliability. The redundant area is already prepared to assume functionality if needed, simplifying the operational complexity while maintaining device reliability.
Data Source
AI summary
Examples of the present disclosure provide a memory device and an operation method thereof, a memory system and a storage medium. The memory device includes: a memory cell array, and a peripheral circuit coupled with the memory cell array, wherein the peripheral circuit is configured to: before performing a power on reset operation, set all state information of a plurality of main memory areas in a page buffer to a normal state; in the process of performing the power on reset operation, match a second address of each of the plurality of main memory areas with a first address in a register; and determine, according to a match result, whether to modify state information of a respective main memory area in the page buffer to a fault state.