NAND Memory Precharge Control for Partial Cell String Programming

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Solution Overview

Problem

Existing memory devices face challenges in improving program performance, particularly in precharge operations, where existing methods fail to optimize the efficiency of data transfer and storage.

Innovation Solution

The implementation of a memory device includes a precharge control circuit that controls a precharge operation and a row decoder to manage word line voltages during precharge, enhancing program efficiency by applying turn-on voltages to selection and adjacent word lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional precharge operation is performed on all cell strings, then data transfer reliability is improved, but program performance and efficiency deteriorate due to unnecessary operations on already-charged strings

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoidprogram performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies different precharge strategies to different cell strings based on their specific needs. The precharge control circuit identifies which cell strings require precharge and applies turn-on voltage only to those strings, rather than uniformly precharging all cell strings. This localized approach maintains data transfer reliability for strings that need it while avoiding unnecessary operations on strings that are already properly charged, thereby improving overall program performance.

Inventive Principle:
Principle #3Local quality

2Productivity

If turn-on voltage is applied to all word lines during precharge, then boosting efficiency is improved, but energy consumption and program time worsen due to unnecessary voltage application

Engineering Contradiction:
Improveboosting efficiencyVSAvoidenergy consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements partial action by applying turn-on voltage only to the specific word lines that are adjacent to or associated with cell strings requiring precharge, rather than applying voltage to all word lines. The precharge control circuit selectively activates only the necessary portion of the word line array, achieving sufficient boosting efficiency for the targeted cell strings while minimizing energy consumption and reducing overall program time by avoiding excessive voltage application to unrelated word lines.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If precharge operation is performed on all cell strings, then data transfer completeness is improved, but program operation time worsens due to extended precharge duration

Engineering Contradiction:
Improvedata transfer completenessVSAvoidprogram operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary identification of which cell strings require precharge before executing the precharge operation. The precharge control circuit determines the specific set of cell strings that need precharging based on their charge status, and then applies turn-on voltage only to the associated word lines. This preliminary selection approach ensures data transfer completeness for the necessary cell strings while significantly reducing program operation time by eliminating unnecessary precharge operations on already-charged strings.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250342887A1Memory device with improved program performance and method of operating the same
Publication Date: 2025.11.06 SAMSUNG ELECTRONICS CO LTD
  • US20250342887A1 patent drawing
  • US20250342887A1 patent drawing
  • US20250342887A1 patent drawing

AI summary

A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.