3D NAND Word Line Pre-Charge Control for Program Disturb

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Solution Overview

Problem

As the number of layers in 3D NAND flash memory increases, the bit density improves, but the program disturb issue worsens, and traditional methods to enhance bit line pre-charge effect, such as extending pre-pulse time or increasing voltage, either sacrifice data programming time or increase transistor breakdown risk.

Innovation Solution

Applying word line pre-pulse signals with different voltage levels and timing to unselected memory strings to enhance channel potential gradient and improve pre-charge effect, thereby reducing programming disturb.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bit line pre-pulse time is extended to improve the pre-charge effect, then the pre-charge effect is improved, but the data programming time is sacrificed

Engineering Contradiction:
Improvepre-charge effectVSAvoiddata programming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The word line pre-pulse signals are segmented into multiple levels (first voltage level and second voltage level) applied at different times. The first word line pre-pulse signal is applied before the second word line pre-pulse signal, creating staged pre-charge that improves effectiveness without proportionally increasing total time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies dynamic voltage levels to word line pre-pulse signals based on the position of word lines relative to the selected word line. Word lines farther from the selected word line receive higher voltage levels, creating a gradient that optimizes pre-charge effect across different regions of the memory array.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the voltage level of the bit line pre-pulse is increased to improve the pre-charge effect, then the pre-charge effect is improved, but the risk of transistor breakdown is increased

Engineering Contradiction:
Improvepre-charge effectVSAvoidtransistor breakdown risk
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Different voltage levels are applied to different word lines based on their local position in the array. Word lines farther from the selected word line receive higher voltage levels than those closer to it, creating a localized gradient that improves pre-charge effect where needed without uniformly increasing stress across all transistors.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the voltage level parameter of word line pre-pulse signals dynamically based on word line position. The control circuit adjusts voltage levels between first and second levels depending on the distance from the selected word line, optimizing the balance between pre-charge effectiveness and transistor safety.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If more layers are added to increase bit density, then the storage capacity is improved, but the program disturb is worsened

Engineering Contradiction:
Improvebit densityVSAvoidprogram disturb
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The word lines are segmented into multiple groups based on their distance from the selected word line, with each group receiving different voltage levels. This segmentation allows targeted pre-charge to unselected word lines, reducing cross-talk and program disturb in deeper layers of the 3D stack.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of control by applying different voltage levels along the vertical dimension (word line depth from selected word line). This creates a voltage gradient that compensates for the increased channel length effect in deeper layers, improving pre-charge effectiveness as layers increase.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12512145B2Non-volatile memory device and control method
Publication Date: 2025.12.30 YANGTZE MEMORY TECH CO LTD
  • US12512145B2 patent drawing
  • US12512145B2 patent drawing
  • US12512145B2 patent drawing

AI summary

A non-volatile memory device includes a memory string, a select gate line coupled to the memory string, word lines coupled to the memory string and including a selected word line, and a control circuit coupled to the select gate line and the word lines, and configured to apply word line pre-pulse signals to at least two groups of the word lines disposed between the select gate line and the selected word line during a pre-charge period. The at least two groups of the word lines include a first group and a second group disposed between the first group and the select gate line. A voltage level of a second word line pre-pulse signal applied to the second group is greater than a voltage level of a first word line pre-pulse signal applied to the first group. A voltage level of at least one word line pre-pulse signal of the word line pre-pulse signals is greater than 0.