NAND String Pre-Charge Ramp-Down to Prevent Program Disturb
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Solution Overview
Problem
Existing non-volatile memory systems face challenges in maintaining narrow threshold voltage distributions to prevent program disturb and ensure reliable data storage, leading to errors in programmed memory cells.
Innovation Solution
The proposed solution involves staggering the ramping down of voltages during the pre-charging process in non-volatile memory systems, specifically by controlling the voltages applied to control lines connected to NAND strings, to prevent program disturb and maintain narrow threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltages are ramped down simultaneously during pre-charging, then the pre-charging process is simple and fast, but program disturb occurs and threshold voltage distributions widen
Solution Approach 1:
The patent segments the voltage ramp-down process by applying different ramp-down timings to different control lines. Specifically, the first control line is ramped down at a different time than the second control line during the pre-charging phase. This segmentation prevents simultaneous voltage transitions that cause program disturb, thereby maintaining narrow threshold voltage distributions and improving data storage reliability without requiring complex additional hardware.
Solution Approach 2:
The patent implements dynamic voltage control by adjusting the ramp-down timing of control lines based on their specific positions and roles in the memory array. The control circuit dynamically modifies the voltage transition schedule for different control lines (e.g., word lines, bit lines, source lines) to optimize the pre-charging process. This dynamic approach prevents program disturb while maintaining operational simplicity.
2Reliability
If standard pre-charging is used, then the programming process is fast, but threshold voltage distributions widen causing program disturb
Solution Approach 1:
The patent applies preliminary action by performing asymmetric voltage ramp-down during the pre-charging phase, before the actual programming operation begins. By ramping down the first control line before the second control line, the system prepares the memory cells in a state that prevents program disturb during subsequent operations. This preliminary asymmetric voltage transition maintains narrow threshold voltage distributions without significantly extending the overall programming time.
Data Source
AI summary
In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including ramping down control lines on a first side of the edge word line, ramping down the edge word line, and performing a staggered ramp down of three or more control lines on a second side of the edge word line. After the pre-charging, unselected NAND strings have their channel boosted to prevent programming and selected NAND strings experience programming on selected memory cells.