3D NAND Conductive Structure Profile for Lower Capacitive Coupling

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Solution Overview

Problem

In microelectronic device fabrication, particularly for 3D NAND Flash memory devices, reducing feature spacing leads to undesirable electrical coupling effects, such as capacitive coupling, which increases programming time and affects high-speed memory performance.

Innovation Solution

The method involves forming microelectronic devices with specific geometric configurations of conductive structures and dielectric materials, including pillar contact structures and plug structures with arcuate profiles, to minimize capacitive coupling between neighboring features, thereby reducing conductive line capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If feature spacing is reduced to increase integration density, then device density is improved, but capacitive coupling between neighboring features increases

Engineering Contradiction:

Improvedevice densityVSAvoidcapacitive coupling

Core Design Contradiction:

Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The conductive structures are formed with arcuate (curved) side surfaces instead of straight vertical walls. This curvature reduces the lateral extent of the conductive structures at intermediate heights, thereby reducing capacitive coupling between neighboring structures while maintaining vertical connectivity and device density.

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The dielectric material is selectively removed to form recesses at specific locations between conductive structures. This creates non-uniform dielectric distribution where the coupling path is weakened locally at critical interfaces, reducing overall capacitive coupling while preserving structural integrity elsewhere.

Inventive Principle:

Principle #3Local quality

2Area of moving object

If conductive structures are placed closer together to reduce area, then area is reduced, but electrical coupling effects increase

Engineering Contradiction:

Improvedevice areaVSAvoidelectrical coupling

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

By forming conductive structures with arcuate side surfaces that curve inward, the lateral footprint of each structure is reduced at intermediate heights. This allows structures to be placed closer together horizontally while maintaining adequate electrical isolation, thus reducing device area without compromising reliability.

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

Dielectric material is retained in recesses between conductive structures, acting as an intermediary that provides electrical isolation. This mediator allows conductive structures to be positioned closer together while preventing harmful electrical coupling, thus reducing area while maintaining reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Quantity of substance

If vertical memory array area is reduced to increase density, then density is improved, but programming time margin is reduced due to capacitive coupling

Engineering Contradiction:

Improvememory densityVSAvoidprogramming time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The arcuate profiles of conductive structures reduce their lateral extent at intermediate heights, minimizing capacitive coupling between neighboring structures. This reduction in capacitive coupling decreases the programming time required while maintaining high memory density through compact vertical array configuration.

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

Selective removal of dielectric material creates localized recesses that reduce capacitive coupling at critical interfaces between conductive structures. This local modification reduces overall programming time while preserving the high-density vertical memory array architecture.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20240170405A1Methods of forming microelectronic devices, and related memory devices and electronic systems

Publication Date: 2024.05.23 MICRON TECHNOLOGY INC

AI summary

A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises a lower portion having a first horizontal width, an upper portion vertically overlying the lower portion and having a second horizontal width greater than the first horizontal width, and an additional portion vertically interposed between the lower portion and the upper portion and having arcuate horizontal boundaries defining additional horizontal widths varying from the first horizontal width proximate the lower portion to a relatively larger horizontal width proximate the upper portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.