3D NAND Program Bias Control for Temperature-Induced Disturbance
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Solution Overview
Problem
3D NAND Flash memory devices experience program disturbance due to the imbalance between Fowler-Nordheim tunneling and hot carrier injection effects, which are exacerbated by temperature changes, affecting read operations and increasing failure bit counts.
Innovation Solution
A temperature-dependent source/drain bias scheme dynamically adjusts bias voltages based on the memory device's temperature to balance the FN tunneling and HCl effects, reducing program disturbance by varying the source and/or drain bias as temperature changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed bias voltage is applied to the bit line or source line during program operation, then the program operation can be performed, but program disturbance occurs due to temperature changes affecting the balance between FN tunneling and HCl effects
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed bias voltage to a dynamic, temperature-dependent bias voltage. The peripheral circuit monitors temperature changes and adjusts the bias voltage applied to the bit line or source line accordingly, allowing the system to adapt to varying thermal conditions during program operations and maintain optimal performance across different temperatures.
Solution Approach 2:
The patent implements parameter changes by modifying the bias voltage parameter based on temperature. The system changes the voltage level dynamically in response to temperature variations, ensuring that the bias voltage remains optimized for the current thermal state. This parameter adjustment compensates for temperature-induced imbalances between FN tunneling and HCl effects, reducing program disturbance.
2Device complexity
If temperature variations are not compensated, then the device structure remains simple, but program disturbance increases due to imbalance between FN tunneling and HCl effects
Solution Approach 1:
The patent employs feedback by implementing a temperature monitoring mechanism that continuously tracks temperature changes and uses this information to adjust the bias voltage. The peripheral circuit receives temperature data and dynamically modifies the voltage applied to the bit line or source line, creating a closed-loop control system that automatically compensates for thermal effects and maintains program operation reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The scheme effectively mitigates program disturbance by compensating for temperature variations, improving the reliability of 3D NAND Flash memory devices by reducing both FN tunneling and HCl-induced errors.
Implementation Method 1
3D NAND Flash memory devices experience program disturbance due to the imbalance between Fowler-Nordheim tunneling and hot carrier injection effects
Implementation Method 2
3D NAND Flash memory devices experience program disturbance due to the imbalance between Fowler-Nordheim tunneling and hot carrier injection effects
Data Source
AI summary
In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, memory cells, and a source select gate (SSG) transistor, a bit line coupled to the DSG transistors, a source line coupled to the SSG transistor, and a peripheral circuit coupled to the memory string through the bit line and the source line. The peripheral circuit is configured to, in a pre-charge period of a program operation, apply a bias voltage to at least one of the bit line or the source line. The bias voltage is determined based on a temperature associated with the memory device.