3D NAND Program Recovery to Reduce Hot-Electron Disturbance

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Solution Overview

Problem

Non-volatile memory devices experience programming disturbances due to high voltages during program operations, leading to hot-electron injections and incorrect data readouts, especially in 3D NAND flash memory with increased word line resistance and reduced programming times.

Innovation Solution

Implementing a faster program recovery phase by turning off the select gate drain (SGD) and turning on the select gate source (SGS) during specific intervals to reduce lateral channel potential gradient, thereby mitigating hot-electron disturbances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high voltage is applied during program operations to improve programming speed, then programming time is reduced, but programming disturbances and hot-electron injections increase

Engineering Contradiction:

Improveprogramming speedVSAvoidprogramming disturbances

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The program recovery phase is divided into multiple sub-phases (first sub-phase and second sub-phase) with different voltage configurations. During the first sub-phase, the selected word line is ramped down while the drain side adjacent word line is held at a higher voltage. During the second sub-phase, the drain side adjacent word line is ramped down. This segmentation allows controlled voltage transitions that reduce hot-electron injections while maintaining programming effectiveness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The program recovery phase is implemented as a preliminary action immediately following the program phase. By proactively applying controlled voltage ramps and holding strategies before reading data, the patent prevents hot-electron disturbances from occurring in the first place, rather than attempting to correct them afterward.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If program recovery time is extended to reduce hot-electron disturbances, then data integrity improves, but programming time increases

Engineering Contradiction:

Improvedata integrityVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The voltage levels and gate configurations are dynamically adjusted during the program recovery phase. The selected word line voltage is ramped down at a controlled rate, and the drain side adjacent word line voltage is held high during the first sub-phase then ramped down during the second sub-phase. This dynamic voltage control reduces hot-electron disturbances while minimizing the recovery time required.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes multiple voltage parameters during the program recovery phase: the selected word line voltage is ramped down from program voltage to a lower level, the drain side adjacent word line voltage is held at a higher voltage during the first sub-phase then ramped down during the second sub-phase, and select gate voltages are adjusted. These coordinated parameter changes reduce hot-electron injections while maintaining a short recovery time.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances program performance by reducing programming disturbances and improving data integrity in memory devices, particularly in high-density 3D NAND flash memory.

Implementation Method 1

programming disturbances due to high voltages during program operations, leading to hot-electron injections

Methodology Applied

Scientific EffectHot-electron injection:

Implementation Method 2

reducing lateral channel potential gradient, thereby mitigating hot-electron disturbances

Methodology Applied

Scientific EffectLateral channel potential gradient: Electric Field

Data Source

PatentUS12481452B2Fast program recovery with reduced programing disturbance in a memory device

Publication Date: 2025.11.25 MICRON TECHNOLOGY INC

AI summary

A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.