3D NAND Program Verify Level Adjustment for Read Window Degradation
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Solution Overview
Problem
Memory devices experience reliability issues due to read window budget degradation, leading to increased bit errors as partially functional blocks in 3D NAND devices face challenges in maintaining accurate read results during program verify phases, especially with increased program erase cycles.
Innovation Solution
A memory sub-system adaptively adjusts the default program verify level during the program verify phase by determining the type of partially functional blocks and applying program verify level adjustments based on the number of program erase cycles, using a program verify level adjustment data structure to compensate for potential read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the default program verify level is used during program verify phase, then the read operation is simple and fast, but read window budget degradation occurs leading to increased bit errors in partially functional blocks
Solution Approach 1:
The patent applies preliminary action by determining the type of partially functional blocks before performing the program verify phase, and pre-calculating the program verify level adjustment value based on the number of program erase cycles. This allows the adjusted program verify level to be applied during the program verify phase without adding complexity to the read level optimization process, thereby preventing read window budget degradation and reducing bit errors.
2Reliability
If program verify level adjustment is applied to compensate for read errors, then bit error rate decreases, but the processing complexity increases
Solution Approach 1:
The patent applies local quality by determining the specific type of partially functional block (e.g., lower deck functional block vs. upper deck functional block) and applying different program verify level adjustments accordingly. The adjustment value is determined based on the number of program erase cycles and the logical state of the memory cell, allowing targeted compensation for read errors in specific block types without unnecessarily complicating the overall system.
3Productivity
If the memory device operates with increased program erase cycles, then storage capacity and durability improve, but read window budget degradation accelerates causing more bit errors
Solution Approach 1:
The patent applies feedback by using the number of program erase cycles as a parameter to determine the program verify level adjustment value. As the memory device undergoes more program erase cycles, the system feedback-adjusts the program verify level to compensate for the cumulative read window budget degradation, thereby maintaining read accuracy even as storage durability increases through extended operation.
Data Source
AI summary
A request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. A program verify level adjustment value based on a number of program erase cycles (PECs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. A default program verify level is adjusted by the program verify level adjustment value to generate an adjusted program verify level. The program operation on the set of vertically stacked memory cells is performed using the adjusted program verify level.