NAND Programming Double-Pulse Technique for CS2 Disturb

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Solution Overview

Problem

NAND memory arrays experience program disturb failures due to the two-sided column-stripe (CS2) data pattern, which degrades boosting efficiency and causes junction leakage, leading to data loss during programming.

Innovation Solution

Implementing a programming process that accounts for CS2 data patterns by using a double-pulse programming technique, where two programming pulses are applied sequentially to memory cells separated by a boosted channel, and determining the need for this technique based on progress through the programming process, programming voltage, or detection of CS2 patterns to reduce the occurrence of CS2 disturb failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional single-pulse programming is used, then programming speed is improved, but program disturb failures occur due to CS2 data patterns

Engineering Contradiction:

Improveprogramming speedVSAvoidprogram disturb failure

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The programming process is segmented into multiple pulses instead of a single pulse. The patent applies a first programming pulse to program selected memory cells, then applies a second programming pulse after a delay period. This segmentation allows the system to detect and handle CS2 data patterns that cause program disturb failures, while maintaining high programming throughput by processing multiple pages in parallel across different memory arrays.

Inventive Principle:

Principle #1Segmentation

2Reliability

If double-pulse programming is applied to all pages, then program disturb failures are eliminated, but programming time increases

Engineering Contradiction:

Improveprogram disturb failureVSAvoidprogramming time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The programming approach is made dynamic by determining whether to apply double-pulse or single-pulse programming based on the specific page's data pattern. The system detects CS2 data patterns and dynamically selects the appropriate programming method: double-pulse for pages with CS2 patterns to prevent program disturb failures, and single-pulse for other pages to maintain fast programming speed. This dynamic adaptation eliminates unnecessary time delays while ensuring reliability where needed.

Inventive Principle:

Principle #15Dynamics

3Productivity

If programming voltage is increased to overcome junction leakage, then programming efficiency is improved, but CS2 disturb failures increase

Engineering Contradiction:

Improveprogramming efficiencyVSAvoidCS2 disturb failure

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system performs preliminary detection of CS2 data patterns before programming. By identifying pages with CS2 patterns in advance, the system can pre-apply the second programming pulse at an appropriate time during the programming sequence. This preliminary action prevents junction leakage-induced failures without requiring excessive programming voltage, as the timing and sequencing of multiple pulses naturally compensates for the reduced efficiency caused by CS2 patterns.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively eliminates CS2 disturb failures by improving boosting efficiency and reducing the probability of program disturb errors, ensuring reliable data programming in NAND memory arrays.

Implementation Method 1

applying a programming voltage or series of programming voltage pulses to the control gates of the selected memory cells

Methodology Applied

Scientific EffectElectrical field effect: Electric Field

Implementation Method 2

generate a channel of carriers by capacitive coupling in the unselected memory cells

Methodology Applied

Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS8102712B2NAND programming technique

Publication Date: 2012.01.24 INTEL NDTM US LLC

AI summary

A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided column-stripe (CS2) data pattern. The CS2 data pattern comprises a memory cell that is not to be programmed directly between two memory cells that are to be programmed, such that a channel associated with the memory cell that is not to be programmed has an applied boost voltage, and the channels associated with the two memory cells that are to be programmed have an applied programming voltage. The first memory cell of the two memory cells is programmed by the first programming voltage pulse and the second memory cell is programmed by the second programming voltage pulse. A programming voltage Vpgm is applied as a single pulse if a CS2 data pattern is not formed.