NAND Memory Programming Latch Reduction via Segmented Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D-NAND memory devices require a large number of latches for programming triple level cells, which increases complexity and costs, and existing methods do not efficiently manage the verification and programming processes to optimize memory cell states.
Innovation Solution
A method and apparatus for programming triple level cells in a 3D-NAND memory device using a cache circuit with reduced latches, where inhibit information is stored and used to apply programming and verification voltages, allowing for non-destructive mode programming and reduced latch requirements, enabling efficient verification and programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of latches are used for programming triple level cells, then the programming capability is improved, but the device complexity and costs increase
Solution Approach 1:
The patent segments the programming process into multiple verification steps (first state verification, second state verification, third state verification) that can be performed sequentially. This allows the system to use fewer latches by reusing the same latch circuits for different verification stages, rather than requiring dedicated latches for each state. The segmentation of the programming workflow enables reduced hardware complexity while maintaining full programming capability.
Solution Approach 2:
The patent implements multi-functional latch circuits that can serve multiple purposes: storing inhibit information, storing verification results, and storing programming data. The same latch circuits are reused across different verification states and operations, eliminating the need for separate dedicated latches for each function. This universal usage of latch circuits directly reduces the total number of latches required in the system.
2Manufacturing precision
If multiple verification operations are performed, then the programming precision is improved, but the loss of time increases
Solution Approach 1:
The patent performs preliminary verification operations at each programming state (first state verification after first state programming, second state verification after second state programming, etc.) before proceeding to the next state. This staged verification approach allows early detection of programming failures, preventing wasted time on subsequent verification operations that would inevitably fail. By verifying incrementally at each state, the system achieves high programming precision while minimizing total verification time.
Solution Approach 2:
The patent implements a conditional flow that allows skipping of subsequent verification operations when earlier verification fails. If the first state verification fails, the system can skip the second and third state verifications entirely, rushing through the remaining steps. This selective skipping mechanism maintains programming precision by ensuring proper verification when needed, while significantly reducing time loss by avoiding redundant verification operations when programming has already failed.
Data Source
AI summary
A method for operating a memory device is disclosed. An inhibit information is set to a first latch. An first programming voltage is applied to word lines of memory cells to program the memory cells. The inhibit information in the first latch is inverted to form a first information. A verification operation is applied on the memory cells, and a second information is stored in the first latch according to the first information and the verification operation. After the verification operation, the second information is inverted in the first latch.