3D NAND Programming Control for Soft Erase and Pass Disturbance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory devices, particularly three-dimensional structures like vertical NAND flash memory, face issues with increased program disturbance and performance degradation due to the smaller channel size and critical dimension, leading to soft erase and hot carrier injection phenomena.
Innovation Solution
The proposed solution involves precharging the channels of cell strings through ground selection transistors, applying program and pass voltages during specific periods, and recovering voltages to negative levels to prevent or reduce soft erase and hot carrier injection, enhancing boosting efficiency and reducing pass disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration degree and memory capacity are increased in three-dimensional nonvolatile memory devices, then storage density is improved, but program disturbance and performance degradation increase due to smaller channel size and critical dimension
Solution Approach 1:
The patent applies preliminary action by precharging the channel to a first voltage through ground selection transistors before the programming operation. This precharging step prepares the channel in an optimal state that prevents soft erase and hot carrier injection phenomena during subsequent programming, thereby addressing program disturbance issues that arise from increased integration density
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting channel voltage levels during different programming phases. The channel voltage is precharged to a first voltage, then boosted to a second voltage during programming, and finally recovered to a third voltage. These parameter changes optimize programming efficiency while preventing performance degradation in high-density memory structures
2Productivity
If channel voltage is boosted during programming to improve programming efficiency, then programming speed is improved, but hot carrier injection and soft erase phenomena occur causing performance degradation
Solution Approach 1:
The patent applies periodic action by implementing distinct programming phases with different voltage conditions: a bit-line setup period with channel precharging to a first voltage, a programming execution period with voltage boosting to a second voltage, and a recovery period with voltage reduction to a third voltage. This periodic voltage modulation achieves high programming efficiency while preventing hot carrier injection and soft erase through proper voltage recovery
Solution Approach 2:
The patent implements feedback by monitoring channel voltage levels and adjusting voltages applied to word lines and bit lines accordingly. The control circuit responds to channel voltage conditions by applying appropriate pass voltages to unselected word lines and adjusting bit-line voltages, thereby maintaining reliable memory cell operation during high-speed programming operations
3Object-affected harmful factors
If negative voltage is applied to unselected word lines to prevent program disturbance, then program disturbance is reduced, but boosting efficiency decreases
Solution Approach 1:
The patent applies local quality by differentiating voltage treatment between selected and unselected word lines. Unselected word lines receive a program pass voltage during the programming execution period that is optimized to minimize pass disturbance, while the selected word line receives the full program voltage. This localized voltage optimization reduces pass disturbance without significantly impacting overall boosting efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes channel voltages, preventing soft erase and hot carrier injection, thereby improving the programming efficiency and reducing program disturbance in nonvolatile memory devices.
Implementation Method 1
precharging the channels of cell strings through ground selection transistors
Implementation Method 2
applying program and pass voltages during specific periods
Implementation Method 3
recovering voltages to negative levels to prevent or reduce soft erase and hot carrier injection
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.