3D NAND Program Pulse Ramping for Slow Word Line Accuracy

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Solution Overview

Problem

Non-volatile memory systems with three-dimensional NAND structures face challenges in maintaining consistent programming speeds across different layers due to tapering memory holes, leading to uneven programming times and potential over-programming errors.

Innovation Solution

Implementing a control mechanism to identify slow word lines and apply a higher program kick voltage for a specific duration during programming loops, adjusting the programming pulse to compensate for varying programming speeds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a uniform program voltage is applied to all word lines, then the programming process is simple to implement, but slow word lines cannot be properly programmed leading to over-programming errors

Engineering Contradiction:

Improveprogramming accuracyVSAvoidprogramming control complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different program voltages to different word line groups based on their specific programming characteristics. Fast word lines receive a first program voltage while slow word lines receive a second program voltage, allowing each group to be programmed with optimized parameters tailored to their individual needs, thereby improving programming accuracy without excessive complexity

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent divides all word lines into multiple groups (fast and slow) based on their programming speed characteristics. This segmentation allows the programming controller to apply different voltage levels to different groups, addressing the reliability issue by ensuring each group receives appropriate programming conditions while managing complexity through systematic classification

Inventive Principle:

Principle #1Segmentation

2Productivity

If the program voltage is increased to speed up programming, then programming speed improves, but over-programming errors increase

Engineering Contradiction:

Improveprogramming speedVSAvoidprogramming accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent changes the program voltage parameter based on word line group characteristics. By setting different voltage levels (first program voltage for fast word lines, second program voltage for slow word lines), the system optimizes programming speed for each group while preventing over-programming, thus resolving the contradiction between speed and accuracy

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The programming system dynamically adjusts the program voltage applied to different word line groups based on their programming speed characteristics. This dynamic adaptation allows fast word lines to be programmed quickly with lower voltage while slow word lines receive higher voltage to achieve comparable programming speeds without over-programming

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12494255B2Real time ramp rate adjustment for better performance and current consumption tradeoff

Publication Date: 2025.12.09 SANDISK TECHNOLOGIES LLC

AI summary

A memory apparatus includes memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to identify ones of the plurality of word lines as slow word lines. The control means is also configured to ramp at least one program pulse applied to the slow word lines to a program kick voltage higher in magnitude than a program voltage for a program kick period of time during at least one program loop of a program operation.