NAND Memory Read Control Using Adaptive ECC Decoding Levels
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Solution Overview
Problem
Non-volatile memory devices face challenges in error correction when memory cell deterioration is severe, leading to increased latency and reduced reliability in data recovery due to the limitations of existing error correction codes.
Innovation Solution
A controller and storage device system that includes an error correction circuit capable of predicting memory cell distributions and selecting appropriate error correction decoding levels based on side information received from non-volatile memory devices, performing adaptive defense code operations such as on-chip valley searches and switching between hard decision, soft decision, and valley search read operations to optimize error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction codes are used for severe memory cell deterioration, then error correction capability is maintained, but latency increases and reliability decreases
Solution Approach 1:
The patent implements dynamic selection of error correction decoding levels based on predicted memory cell distribution. The controller adapts the error correction strategy in real-time by switching between multiple decoding levels (e.g., first level for mild deterioration, second level for severe deterioration) according to the actual state of memory cells, rather than using a fixed traditional ECC approach. This dynamic adaptation resolves the contradiction by optimizing both reliability and latency according to actual conditions.
Solution Approach 2:
The system changes the parameter of error correction decoding level based on predicted memory cell distribution characteristics. By analyzing side information and predicting whether memory cells are in a deteriorated state, the system adjusts the decoding level parameter to match the actual error rate, thereby improving data recovery reliability while minimizing unnecessary latency from over-correction.
2Reliability
If adaptive defense code operations are implemented with multiple decoding levels, then data recovery reliability improves, but device complexity increases
Solution Approach 1:
The error correction function is segmented into multiple independent decoding levels, each optimized for specific deterioration scenarios. The controller divides the error correction process into discrete stages (first decoding level, second decoding level, etc.), where each level can be independently selected and executed. This segmentation allows the system to achieve high reliability through multiple correction strategies while managing complexity by only activating the necessary level for each situation.
Solution Approach 2:
The error correction circuit is designed with multi-functionality to handle various deterioration levels using the same hardware infrastructure. The universal error correction circuit can operate at different decoding levels depending on the predicted memory cell distribution, eliminating the need for separate dedicated circuits for each correction scenario and thereby reducing overall device complexity while maintaining high reliability.
Data Source
AI summary
A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.