NAND Memory Read Bias Control to Prevent Premature Verification
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in scaling down NAND memory devices while maintaining threshold voltage margin, leading to increased circuit area and energy consumption without a corresponding improvement in performance.
Innovation Solution
A method of programming memory cells in multiple program loops, where the bit line voltage and pass voltage are adjusted during early loops to prevent premature verification by artificially elevating current in the memory strings, thereby ensuring accurate programming without increasing threshold voltage margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND memory devices are scaled down to improve density, then storage capacity increases, but threshold voltage margin deteriorates
Solution Approach 1:
The patent applies preliminary action by adjusting bit line and pass voltages before verification occurs in early program loops. This preemptive voltage adjustment prevents premature verification by controlling the current flow in memory strings, ensuring that verification only occurs when threshold voltage has reached the appropriate level. This approach maintains threshold voltage margin during device scaling without requiring additional circuit area.
2Reliability
If traditional programming methods are used to maintain threshold voltage margin, then reliability is preserved, but programming accuracy deteriorates due to premature verification
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting bit line voltage and pass voltage based on the program loop stage. In early program loops, elevated voltages prevent premature verification, while in later loops, standard voltages restore normal verification. This time-dependent parameter adjustment ensures both threshold voltage margin preservation and programming accuracy without compromising either reliability or measurement precision.
3Measurement precision
If voltage adjustments are applied in early program loops, then programming accuracy improves, but energy consumption increases
Solution Approach 1:
The patent applies periodic action by implementing voltage adjustments only during early program loops when premature verification is most likely to occur. Once the memory cells have been programmed sufficiently, the adjusted voltages are discontinued and standard verification voltages are restored. This time-limited approach achieves programming accuracy improvement while minimizing additional energy consumption by applying elevated voltages only when necessary.
Data Source
AI summary
The memory device an array of memory cells arranged in a word lines and a one common source line (CELSRC) driver. Control circuitry is configured to program the memory cells of a selected word line in a plurality of program loops. During the program loops, the control circuitry sets a voltage of the CELSRC driver to approximately zero Volts, applies a verify voltage to the selected word line, applies a pass voltage to unselected word lines, and applies a bit line voltage to a bit line that is coupled to a memory cell to be sensed. During at least one early program loop for a given data state, the control circuitry increases the bit line voltage or increases the pass voltage. The control circuitry is further configured to reduce the bit line voltage or the pass voltage for the verify operations in at least one subsequent program loop.