Multi-Plane NAND Read Sequence Without Dummy Busy Cycles
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Solution Overview
Problem
NAND-type flash memory systems experience increased latency and performance issues due to dummy busy cycles and column address cycles, which are not scalable with increasing input/output speeds.
Innovation Solution
A 'super lean' read command sequence is implemented that eliminates column address cycles, multi-plane confirm commands, and dummy busy cycles, optimizing data transfer by using a fixed column address and reducing command latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional read command sequence is used to read data from multiple planes, then the read operation can be performed, but the latency increases due to dummy busy cycles and column address cycles
Solution Approach 1:
The patent extracts and removes unnecessary command elements (dummy busy cycles and column address cycles) from the read command sequence. By eliminating these redundant components, the command sequence becomes shorter and more efficient, directly reducing read latency while improving channel efficiency for multi-plane read operations.
Solution Approach 2:
The patent changes the parameter of the read command sequence by fixing the column address and eliminating the need for column address transmission. This parameter change transforms the variable column address approach into a fixed column address approach, reducing the number of command cycles required and improving overall read performance.
2Ease of operation
If the command sequence includes dummy busy cycles and column address transmission, then the read operation can be completed, but the command sequence length increases
Solution Approach 1:
The patent extracts and removes dummy busy cycles and column address transmission from the command sequence. This extraction eliminates unnecessary waiting periods and data transmission steps, directly reducing the command sequence duration while maintaining the essential read operation functionality.
Solution Approach 2:
The patent enables continuous useful action by eliminating dummy busy cycles that create idle waiting periods. The optimized command sequence allows the system to continuously perform useful read operations without interruption, maximizing channel efficiency and reducing overall operation duration.
3Adaptability or versatility
If traditional multi-plane read commands are used, then data can be read from multiple planes, but the number of commands and cycles increases
Solution Approach 1:
The patent applies universality by creating a simplified read command sequence that can handle multiple planes using a fixed column address. This universal approach eliminates the need for separate column address handling for each plane, reducing command sequence complexity while maintaining multi-plane read capability.
Solution Approach 2:
The patent merges the column address information into a fixed value that applies to all planes, combining what would otherwise be separate address specifications. This merging reduces the number of individual commands and cycles needed, simplifying the overall command sequence while preserving multi-plane access functionality.
Data Source
AI summary
Systems, apparatuses and methods may provide for technology that generates address information for a plurality of planes in NAND memory, excludes column information from the address information, and sends a read command sequence to the NAND memory, wherein the read command sequence includes the address information. In one example, the technology also excludes plane confirm commands and busy cycles from the read command sequence.