Hierarchical Read Counter Mitigates NAND Flash Disturb
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Solution Overview
Problem
Current memory systems using NAND flash memory face challenges in maintaining data reliability due to read disturb issues, where frequent read operations can lead to unexpected increases in threshold voltage of memory cells, causing errors that traditional error correction mechanisms may not be able to correct.
Innovation Solution
A memory system with a controller that counts the number of read operations for each memory unit and performs a refresh operation by rewriting data when a predetermined threshold is reached, using a hierarchical counter system to manage and mitigate the effects of read disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequent read operations are performed on memory units, then data accessibility and read performance are improved, but read disturb effects increase causing threshold voltage shifts and data errors
Solution Approach 1:
The controller performs preliminary actions by monitoring read operation counts in advance and executing refresh operations before threshold voltage shifts become problematic. The system proactively identifies memory units approaching their read operation limit and initiates refresh cycles to prevent read disturb effects from degrading data reliability.
Solution Approach 2:
The system implements feedback mechanisms where the controller continuously monitors the number of read operations for each memory unit and uses this information to determine when refresh operations are needed. This closed-loop approach allows the system to adapt read operation patterns based on actual usage data, maintaining reliability while maximizing productivity.
2Reliability
If traditional error correction mechanisms are used, then data error correction is attempted, but read disturb errors caused by frequent reads cannot be corrected
Solution Approach 1:
Instead of relying solely on post-error correction, the system performs preliminary refresh operations to prevent read disturb errors from occurring in the first place. By monitoring read operation counts and executing refresh cycles proactively, the system eliminates the harmful effects before they can manifest as uncorrectable errors.
Solution Approach 2:
The system converts the potentially harmful effect of frequent read operations into a beneficial monitoring signal. The read operation count, which could be seen as a source of read disturb, is instead used as a metric to trigger protective refresh operations, transforming the problem into a control mechanism that prevents errors.
3Device complexity
If a single counter is used to track read operations, then device complexity is reduced, but accurate tracking of read operation thresholds for individual memory units becomes difficult
Solution Approach 1:
The system segments the counting function by implementing separate counters for each memory unit or group of memory units. This segmentation allows precise tracking of read operation counts at the individual unit level, enabling accurate threshold monitoring and targeted refresh operations without requiring an overly complex centralized counting system.
Data Source
AI summary
A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.