NAND Memory Read Disturb Reduction via Localized Voltage Biasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In non-volatile memory systems with NAND type architecture, determining the last written word line in a partially written block is inefficient, leading to high bit error rates due to read disturb effects on erased word lines, especially when performing binary scans for last written page detection.
Innovation Solution
A method is introduced to reduce read disturb by applying a lower VREAD_PARTIAL voltage to non-selected word lines, allowing only the selected word line to conduct accurately, and using this voltage to determine the last written word line, thereby reducing bit error rates and improving detection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a standard VREAD voltage is applied to all non-selected word lines during read operations, then accurate data reading is achieved, but read disturb effects occur on erased word lines in partially written blocks
Solution Approach 1:
The patent applies different voltage levels to different groups of non-selected word lines based on their write status. Specifically, non-selected word lines in written blocks receive a first VREAD voltage level, while non-selected word lines in partially written blocks receive a second, lower VREAD voltage level. This local differentiation eliminates read disturb effects on erased word lines in partially written blocks while maintaining accurate reading in fully written blocks.
2Difficulty of detecting and measuring
If binary scan is performed to detect the last written page in partially written blocks, then detection capability is improved, but bit error rates increase due to repeated read disturb on erased word lines
Solution Approach 1:
During binary scan operations, the patent implements local quality by applying the reduced VREAD voltage level specifically to non-selected word lines in partially written blocks. This allows the binary scan to proceed effectively for detecting the last written page while minimizing read disturb effects that would otherwise cause high bit error rates on erased word lines.
3Ease of operation
If multiple non-selected word lines are biased to high VREAD voltage during read operations, then all memory cells can conduct independently of data state, but erased word lines in partially written blocks suffer from read disturb
Solution Approach 1:
The patent modifies the read operation by implementing local quality through differentiated voltage biasing. Non-selected word lines in partially written blocks are biased to a lower VREAD voltage level, while non-selected word lines in fully written blocks maintain the standard higher VREAD voltage level. This approach preserves the simplicity of read operations in written blocks while protecting erased word lines in partially written blocks from read disturb effects.
Solution Approach 2:
The patent changes the voltage parameter (VREAD level) applied to non-selected word lines based on the write status of their respective blocks. By dynamically adjusting the voltage parameter from a first level (for written blocks) to a second, lower level (for partially written blocks), the system eliminates read disturb effects while maintaining appropriate read operation characteristics for each block type.
Data Source
AI summary
Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for a read operation, including post-write verify reads. Non-selected word lines that are unwritten are biased with a lower read-pass voltage then is typically used. The determination of the last written word line of a block can be done in a coarse-fine search, where the word lines are divided into a number of zones to find the zone with the last written word line, which is in turn sub-divided for a finer search.