NAND Cold-Read Voltage Tracking to Reduce Read Disturb
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Solution Overview
Problem
Memory cells in semiconductor devices experience read disturbs due to floating word line voltages, which are influenced by the time since the last sensing operation and temperature, leading to increased threshold voltage and interference during read operations.
Innovation Solution
A tracking circuit monitors the floating voltage of unselected word lines to determine if a memory block is in a 'cold' or 'hot' read situation, adjusting the duration and magnitude of the SGD control gate voltage pulse and bit line voltage increase based on the read situation and temperature to minimize disturbs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read operations are performed on memory blocks after a power on event or after a long delay since the last read, then the memory device can access stored data, but floating word line voltages cause hot electron injection type read disturbs that increase threshold voltage and degrade data integrity
Solution Approach 1:
The patent applies preliminary action by performing a first read operation before a second read operation when the memory block is in a cold read situation (after power on or long delay). This first read operation prepares the memory block by establishing proper voltage conditions on word lines and select gates, thereby preventing hot electron injection type read disturbs during subsequent read operations. The tracking circuit detects the cold read condition and triggers this preparatory read sequence.
Solution Approach 2:
The patent implements dynamics by using a tracking circuit that continuously monitors the time since the last read operation and dynamically adjusts the read operation sequence based on the detected read situation. When a cold read situation is detected (time exceeds a threshold), the system dynamically modifies the read sequence to include a preparatory first read operation, thereby adapting to changing memory block conditions and preventing read disturbs.
2Ease of operation
If conventional read operations are used without considering read situation, then the memory device operates with simple fixed sequences, but read disturbs occur in cold read situations leading to increased threshold voltage
Solution Approach 1:
The patent applies feedback by using a tracking circuit that monitors the time since the last read operation and provides feedback about the read situation (cold or hot) to the read operation control logic. Based on this feedback, the system automatically adjusts the read sequence - using a simple sequence for hot reads and a preparatory sequence for cold reads - thereby maintaining threshold voltage stability while adapting operation complexity to actual needs.
Solution Approach 2:
The patent implements parameter changes by modifying the read operation parameters (sequence, timing, voltage application) based on the detected read situation. When a cold read is detected, the system changes the operational parameters to include a preparatory first read operation with specific voltage conditions, thereby preventing threshold voltage shifts without affecting normal hot read operations.
3Measurement precision
If the voltage of unselected word lines is increased during read operations, then sensing of selected memory cells is enabled, but floating channel regions in unselected NAND strings experience hot electron injection causing read disturbs
Solution Approach 1:
The patent applies preliminary anti-action by performing a first read operation before a second read operation in cold read situations. This preparatory operation establishes proper voltage conditions on select gates and word lines, creating a controlled electrical environment that prevents the formation of harmful voltage gradients in unselected NAND strings during the actual sensing operation, thereby counteracting the potential for hot electron injection.
Solution Approach 2:
The patent implements beforehand cushioning by using the first read operation as a buffer that prepares the memory block's electrical state. This preparatory operation cushions against the potential harmful effects of subsequent read operations by ensuring that select gate voltages and word line voltages are properly established, thereby preventing excessive voltage gradients that would cause hot electron injection in unselected strings.
Data Source
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AI summary
A memory device and associated techniques for optimizing the channel boosting level in an unselected NAND string during a read operation for a selected NAND string. A tracking circuit tracks an indicator of a floating voltage of unselected word lines of a block. For example, this can include tracking a time since a last sensing operation, and determining whether a power on event has occurred without a subsequent sensing operation. In response to a read command, the indicator is used to set parameters in the read operation which can reduce disturbs. This can include setting a duration and/or a magnitude of a select gate voltage pulse during the increase of the voltage of the unselected word lines. The duration and/or a magnitude of the control gate voltage pulse can also be set based on a temperature.