3D NAND Memory Read Disturbance Mitigation via Voltage Sequencing
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Solution Overview
Problem
Three-dimensional NAND memory devices with a gate-all-around structure experience read disturbance due to hot carrier effects during read operations, exacerbated by the miniaturization of memory devices and increased operation complexity, leading to elevated threshold voltages of transistors on word lines.
Innovation Solution
A memory device configuration with a P-well region, common source line, ground selection line, dummy ground selection lines, word lines, string selection line, and bit line, where a control circuit applies specific voltage sequences to reduce read disturbance by generating band-to-band hot hole currents in the channel region, including decreasing the voltage of the string and dummy string selection lines before increasing the bit line voltage, thereby eliminating down-coupled channel potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read operations are performed on three-dimensional NAND memory devices with GAA structure, then data can be read from memory cells, but hot carrier effects occur causing threshold voltage increase and read disturbance on word lines
Solution Approach 1:
The patent applies preliminary action by decreasing the voltage of string selection line and dummy string selection line before increasing bit line voltage during read operations. This voltage sequence control prevents hot carrier effects from occurring in the first place, rather than attempting to mitigate them after they occur. By establishing the proper voltage conditions beforehand, the patent eliminates the root cause of threshold voltage increase and read disturbance on word lines.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the voltage levels of string selection line, dummy string selection line, and bit line in a specific sequence during read operations. This parameter control approach changes the electrical conditions in the channel region to generate band-to-band hot hole currents that counteract hot carrier effects, thereby maintaining stable threshold voltages on word lines and preventing read disturbance.
2Productivity
If memory device size is miniaturized to increase storage capacity, then more memory cells can be integrated, but spacing between word lines decreases causing more severe read disturbance
Solution Approach 1:
The patent applies local quality by introducing dummy string selection lines and applying specific voltage sequences to localized regions of the memory device. This targeted approach addresses read disturbance in specific areas where word lines are closely spaced, without affecting the overall high-density structure. The dummy string selection lines create localized electric field conditions that prevent hot carrier effects in critical regions while maintaining the miniaturized high-capacity architecture.
3Adaptability or versatility
If complex operations with increased program and read operations are performed to meet application demands, then computational capability is improved, but read disturbance between word lines becomes more serious
Solution Approach 1:
The patent applies periodic action by implementing a specific voltage sequence that is repeatedly applied during each read operation. The control circuit periodically decreases string selection line voltage, then increases bit line voltage in a cyclic manner for each read access. This periodic voltage modulation ensures that hot carrier effects are consistently prevented across multiple read operations and complex computational workloads, maintaining reliability even as operation frequency increases.
Data Source
AI summary
A memory device and an operation method thereof are disclosed. The memory device includes a P-well region, a common source line, a ground selection line, at least one dummy ground selection line, a plurality of word lines, at least one dummy string selection line, a string selection line, at least one bit line and at least one memory string. The gates of a plurality of memory cells of the memory string are connected to the word lines. The operation method includes the following steps. Performing a read operation and applying a read voltage on the selected word line. Applying a pass voltage on other unselected word lines and the ground selection lines, etc. Before ending of the read operation, firstly decreasing voltages of the string selection line and the dummy string selection line in advance, then increasing voltage of the bit line.