NAND Memory Read Sensing with Fail-Bit Adaptive Dual Pass
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Solution Overview
Problem
Existing semiconductor memory devices face inefficiencies in sensing operations, leading to increased current consumption and prolonged processing times, particularly in NAND memory devices with multiple program loops and verify operations.
Innovation Solution
Implementing a dual-sensing technique that includes a fast read process with positive sensing followed by a slower read process with negative sensing if fail bit count exceeds a threshold, utilizing zero Volts during the first sensing and a positive voltage during the second, while reducing sensing timing parameters and maintaining consistent reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a fast read technique is used during sensing operations, then processing speed is improved, but current consumption increases and fail bit count increases
Solution Approach 1:
The sensing operation is divided into two distinct processes: a first sensing process using fast read technique with positive sensing for initial detection, and a second sensing process using slower read technique with negative sensing for verification when fail bits are detected. This segmentation allows the system to use the faster technique only when necessary while relying on the more energy-efficient technique for routine operations.
Solution Approach 2:
The sensing technique dynamically switches between fast read and slower read modes based on real-time detection of fail bits. The system adjusts the read speed and sensing polarity adaptively - using fast positive sensing initially, then transitioning to slower negative sensing if needed, optimizing the balance between speed and energy consumption based on actual data conditions.
2Speed
If a fast read technique is used during sensing operations, then processing speed is improved, but reliability deteriorates due to increased fail bit count
Solution Approach 1:
The system implements feedback by monitoring fail bit counts during the first sensing process and using this information to determine whether to initiate a second sensing process. When fail bits exceed a threshold, the system triggers a verification pass using negative sensing, ensuring that unreliable fast reads are corrected while maintaining overall system speed through selective re-sensing.
Solution Approach 2:
The patent prepares for potential reliability issues by having a pre-planned second sensing process ready to execute when fail bits are detected. This cushioning approach ensures that if the fast read produces unreliable results, the system can immediately switch to the more reliable slower read technique without compromising overall data integrity.
3Speed
If positive sensing technique is used with fast read, then processing speed is improved, but energy efficiency deteriorates
Solution Approach 1:
The patent applies different sensing qualities to different situations: positive sensing is used locally during the fast first sensing process where speed is prioritized, while negative sensing is applied locally during the second verification process where energy efficiency and reliability are prioritized. This localized application of different sensing qualities optimizes the overall energy-speed tradeoff.
Data Source
AI summary
The memory device includes circuitry which is configured to sense threshold voltages of the memory cells of a selected word line of the plurality of word lines in a sensing operation. During the sensing operation, the circuitry, in a first sensing process, senses the memory cells of the selected word line using both a fast read technique and a positive sensing technique. The circuitry also determines a fail bit count and compares the fail bit count to a threshold. In response to the fail bit count being less than or equal to the threshold, the circuitry completes the sensing operation. In response to the fail bit count exceeding the threshold, then the circuitry performs a second sensing process to sense threshold voltages of the memory cells of the selected word line using a relatively slower read technique.