NAND Memory Read Operation Leakage Mitigation
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Solution Overview
Problem
NAND flash memory devices face significant current leakage issues during read operations due to the coupling of thousands of memory cells to each bit line, which affects accuracy and power consumption as device sizes decrease.
Innovation Solution
The implementation of a read operation method where varying potentials are applied to source lines associated with selected and unselected blocks of memory cells, mitigating leakage by reducing voltage differentials between unselected source lines and selected bit lines, thereby enhancing read accuracy and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device size is decreased to increase memory density, then memory density is improved, but current leakage increases
Solution Approach 1:
The patent applies different voltage potentials to different source lines based on their association with selected or unselected blocks. Source lines associated with selected blocks receive a first potential (e.g., 0V), while source lines associated with unselected blocks receive a second potential (e.g., 1V or higher). This local differentiation of voltage conditions reduces leakage current from unselected blocks without affecting the read operation of selected blocks, thereby maintaining memory density while reducing overall current leakage.
2Quantity of substance
If thousands of memory cells are coupled to each bit line to increase capacity, then memory capacity is improved, but current leakage during read operations increases
Solution Approach 1:
The patent changes the voltage parameter of source lines dynamically during read operations. By adjusting the potential of source lines associated with unselected blocks to be closer to the bit line potential, the voltage differential is reduced, thereby minimizing leakage current. This parameter change allows the system to maintain high memory capacity while reducing the harmful leakage effect.
Data Source
AI summary
Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to a source line selectively coupled to a bit line through a string of series-coupled non-volatile memory cells containing a memory cell targeted for reading, and where a second, different, potential is supplied to other source lines selectively coupled to the bit line through other strings of series-coupled non-volatile memory cells not containing the target memory cell. Supplying a different potential to the other source lines facilitates mitigation of current leakage between the other source lines and the bit line while sensing a data value of the target memory cell.