3D NAND Read Level Management for Threshold Voltage Drift
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Solution Overview
Problem
Memory devices experience performance degradation over time due to changes in threshold or processing voltage levels, leading to errors and imbalances in stored charge levels across different groupings of memory cells, particularly in 3D NAND architectures.
Innovation Solution
Implementing a read level management mechanism that dynamically adjusts read levels based on real-time conditions, using default, dynamic, and tuning voltages to account for charge imbalances across decks in memory cells, thereby maintaining data integrity and reducing error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory devices store and access data using electrical energy and threshold voltage levels, then data storage and retrieval are enabled, but performance degradation and errors occur over time due to changes in threshold voltage levels
Solution Approach 1:
The patent implements dynamic read level adjustment mechanisms that adapt to changing threshold voltage conditions over time. The system continuously monitors and adjusts read levels to compensate for voltage drift, ensuring reliable data retrieval throughout the device's operational lifespan despite temporal degradation.
Solution Approach 2:
The patent changes the read voltage parameter dynamically based on detected threshold voltage shifts. By adjusting the read level parameter in response to temporal changes in threshold voltage, the system maintains data integrity throughout the device's operational life.
2Adaptability or versatility
If different groupings of memory cells are programmed at different times, then storage capacity and flexibility are improved, but charge imbalances and errors occur due to delays between programming operations
Solution Approach 1:
The patent applies different read levels to different groupings or decks of memory cells based on their specific programming timing and charge characteristics. This localized adjustment ensures that each grouping is read with the optimal voltage level, compensating for charge imbalances caused by staggered programming operations.
Solution Approach 2:
The patent divides memory cells into different groupings or decks that can be programmed independently at different times. By segmenting the memory structure and applying针对性的 read level adjustments to each grouping, the system maintains charge balance and reliability while preserving programming flexibility.
3Reliability
If read level management is implemented to maintain data integrity, then error rates are reduced, but additional processing resources and complexity are required
Solution Approach 1:
The patent implements self-adjusting read level mechanisms where the memory device automatically detects and compensates for threshold voltage changes without requiring external intervention. The system uses built-in monitoring and adjustment capabilities to maintain data integrity independently, minimizing the need for additional processing resources.
Solution Approach 2:
The patent employs feedback mechanisms that monitor read errors and threshold voltage levels, then automatically adjust read levels in response. This closed-loop control system maintains data integrity by continuously adapting to changing conditions while using efficient feedback-based adjustment algorithms to minimize processing overhead.
Data Source
AI summary
Methods, apparatuses and systems related to protecting an apparatus against unauthorized accesses or usages are described. The apparatus may include a data protection circuit that protects an operating state of the apparatus, data stored in the apparatus, or a combination thereof when a temperature of the apparatus is outside of an operating range thereof.