NAND Flash Read-Level Tracking for Asymmetric Vth Distributions

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Solution Overview

Problem

Existing NAND flash memory systems face challenges in accurately determining the optimum read level due to asymmetric threshold voltage distributions of memory cell transistors, leading to increased error bits and reduced data integrity.

Innovation Solution

The memory system employs Vth tracking with adjustable step sizes to estimate the optimum read level by considering the gradient of threshold voltage distribution, minimizing error bits through precise read level adjustments.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional read operations are used with fixed read levels, then the memory system operates simply, but error bits increase due to asymmetric threshold voltage distributions

Engineering Contradiction:
Improvedata integrityVSAvoidread operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic read level adjustment through Vth tracking, where read levels are no longer fixed but adaptively changed based on detected threshold voltage distributions. The memory controller performs multiple read operations with different read levels and dynamically selects the optimal read level that minimizes error bits, directly resolving the contradiction between reliability and complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where the memory controller detects threshold voltage distributions from read operations, compares them against reference distributions, and adjusts subsequent read levels based on this feedback. This closed-loop control system continuously optimizes read levels to maintain data integrity while adapting to changing memory characteristics.

Inventive Principle:
Principle #23Feedback

2Reliability

If Vth tracking with multiple read levels is implemented, then data integrity improves, but processing time increases

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs Vth tracking and read level optimization in advance during idle periods or alongside regular memory operations. By proactively detecting and adjusting threshold voltage distributions before they cause errors, the system maintains high data integrity without adding significant processing time to critical read paths.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The implementation uses periodic sampling of threshold voltage distributions at strategically chosen intervals rather than continuous monitoring. This periodic approach captures essential changes in memory characteristics while minimizing the time overhead, balancing reliability improvement with processing efficiency.

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If fixed step size is used in Vth tracking, then the implementation is simple, but accuracy deteriorates due to asymmetric distributions

Engineering Contradiction:
Improveread level detection accuracyVSAvoidVth tracking complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent explicitly addresses asymmetric threshold voltage distributions by implementing asymmetric step sizes in Vth tracking. Different step sizes are used for upward and downward adjustments, or for different regions of the voltage distribution, directly compensating for the asymmetry and improving measurement precision while maintaining implementation feasibility.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The system applies different step sizes locally based on the specific characteristics of the detected threshold voltage distribution. Rather than using a uniform approach, the Vth tracking adapts its step size to match the local properties of the distribution, enhancing accuracy in each specific operating condition.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12547539B2Memory system and memory device
Publication Date: 2026.02.10 KIOXIA CORP
  • US12547539B2 patent drawing
  • US12547539B2 patent drawing
  • US12547539B2 patent drawing

AI summary

A memory system according to one embodiment includes a memory device and a memory controller. The memory device includes memory cells. The memory controller executes a tracking operation. In the tracking operation, the memory controller is configured to cause the memory device to execute a plurality of times of read operations using a plurality of read levels. In the tracking operation, the memory controller is further configured to set a first voltage difference between two adjacent read levels of the read levels in a fourth voltage range lower than a first voltage in a third voltage range and a second voltage difference between two adjacent read levels of the read levels in a fifth voltage range higher than the first voltage in the third voltage range. The first and second voltage differences are different from each other.