NAND Read Calibration Using Word Line Linear Ramp
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Solution Overview
Problem
Existing memory devices face challenges in efficiently performing read operations due to charge loss mechanisms in replacement-gate NAND memory, leading to increased latency from traditional read level calibration processes.
Innovation Solution
Implementing an auto calibrated read operation that minimizes latency by quickly detecting threshold voltage distributions during a linear word line ramp, using a micro-controller to calibrate read levels based on memory cell activation outputs, and optimizing the read operation with calibrated voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional read level calibration processes are used in replacement-gate NAND memory, then read operations can be performed, but latency increases due to the time-consuming calibration process
Solution Approach 1:
The system performs self-calibration by automatically detecting threshold voltage distributions and adjusting read levels without external intervention. The micro-controller autonomously monitors memory cell activation outputs during word line ramping and dynamically calibrates read levels, eliminating the need for manual calibration processes and reducing latency while maintaining accuracy.
Solution Approach 2:
The calibration process uses feedback from memory cell activation outputs to continuously monitor and adjust read levels. The system detects the distribution of threshold voltages by observing cell activation during word line ramping and uses this feedback information to optimize read levels dynamically, ensuring accurate reads while minimizing calibration time.
2Loss of time
If quick detection of threshold voltage distributions is performed during linear word line ramp, then calibration time is reduced, but measurement precision may be compromised
Solution Approach 1:
The system performs continuous monitoring of memory cell activation outputs throughout the entire word line ramp process. By continuously sampling activation data at multiple points during the ramp, the system accumulates sufficient information to accurately determine threshold voltage distributions without requiring extended calibration periods, thus maintaining precision while reducing time.
Solution Approach 2:
The system uses a linear word line ramp that extends beyond the minimum necessary range, deliberately applying excessive voltage sweep to ensure complete coverage of all threshold voltage distributions. This excessive action guarantees that all memory cells are activated and measured, providing comprehensive data for accurate calibration without requiring multiple separate measurement cycles.
Data Source
AI summary
Methods, systems, and devices for techniques for performing a read operation for memory cells are disclosed herein. A word line voltage level is ramped at a first rate of change. Memory cell activation outputs are detected from a subset of the memory cells based on ramping the word line voltage level at the first rate of change. Word line read levels are calibrated for the memory cells based on the detected memory cell activation outputs. The word line voltage level is ramped at a second rate of change, and data stored in the memory cells activated is read when the word line voltage level ramped at the second rate of change reaches the calibrated word line read levels. A reset program verify operation is not applied to memory cells corresponding to at least one stage of the word line based on previously applied programming pulses or program verify operations.