NAND Flash Read Pipeline With Three-Level Buffering and Split ECC
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Solution Overview
Problem
NAND flash devices experience significant read latency during continuous read operations, which slows down performance compared to other memory types, despite advancements like cache read and continuous read command sequences.
Innovation Solution
A memory device with a three-level buffering system and divided ECC operations, where data is transferred through a page buffer, a second buffer level, and a third buffer level, with ECC functions executed in parallel to reduce latency and enhance throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional continuous read operations are used in NAND flash devices, then data can be read sequentially, but significant read latency remains which slows down performance
Solution Approach 1:
The patent segments the continuous read operation into multiple independent pipeline stages: (1) data transfer from memory array to page buffer, (2) ECC operations on the transferred data, and (3) preparation of next page data. This segmentation allows each stage to operate independently and in parallel, eliminating sequential delays and reducing overall read latency while maintaining continuous read speed.
Solution Approach 2:
The patent performs preliminary actions by initiating ECC operations on currently transferred data while simultaneously preparing the next page data in advance. The page buffer holds incoming page data ready for ECC processing, and the system pre-fetches and pre-processes subsequent pages before they are requested, thereby eliminating waiting time and reducing read latency.
2Reliability
If ECC operations are performed sequentially after data transfer, then error correction is ensured, but throughput is reduced due to lack of overlap between transfer and ECC operations
Solution Approach 1:
The patent implements continuity of useful action by maintaining overlapping ECC operations with data transfer throughout the read process. While data is being transferred from the memory array to the page buffer, ECC operations are continuously performed on previously transferred data. This continuous parallel execution ensures error correction reliability is maintained while maximizing throughput by eliminating idle time.
Solution Approach 2:
The patent introduces dynamic operation modes where the system can adaptively switch between different ECC processing configurations. The controller dynamically manages the timing and资源配置 of ECC operations based on data transfer status, allowing flexible optimization of both reliability and throughput under different operating conditions.
3Device complexity
If a simple buffer structure is used, then device complexity is low, but latency reduction through overlapping operations is limited
Solution Approach 1:
The patent adds temporal dimension to the buffer structure by implementing a multi-stage pipeline architecture. Instead of a single static buffer, the system uses a sequence of buffer stages (memory array → page buffer → output register) that operate at different time points. This dimensional transformation from spatial to temporal organization enables overlapping operations and significantly reduces read latency while keeping each individual buffer stage relatively simple.
Data Source
AI summary
A memory device such as a page mode NAND flash is operated, using a first pipeline stage, to clear a page buffer to a second buffer level, and transfer a page to the page buffer; a second pipeline stage to clear the second buffer level to the third buffer level and transfer the page from the page buffer to the second buffer level; a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing an second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.