Adaptive Read Retry Order for NAND Decoding Error Recovery
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Solution Overview
Problem
Flash memory devices, such as NAND flash memory, experience high error rates due to manufacturing variations and aging, leading to data errors during read operations, which current error correction methods like LDPC and BCH codes attempt to address but introduce unwanted latency.
Innovation Solution
The technology adjusts the read-level voltage sequence based on a decoding success trend to predict error types and optimize read retries, leveraging similarities in read errors among memory cells to improve multi-stage decoding operations and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correcting codes (LDPC and BCH) are applied to correct data errors during read operations, then data error correction capability is improved, but read operation latency increases
Solution Approach 1:
The system performs preliminary actions by maintaining a history of previously successful read-level voltages and their corresponding decoding outcomes. Before attempting error correction with LDPC/BCH codes, the system first checks this historical data to identify voltage levels that have successfully decoded similar data patterns in the past, thereby avoiding unnecessary full error correction cycles and reducing latency
Solution Approach 2:
The system dynamically adjusts the read-level voltage sequence based on real-time decoding feedback and historical success patterns. Instead of using a fixed voltage sequence, the system adapts the voltage levels and ordering based on observed error patterns and successful decoding outcomes, optimizing the balance between error correction effectiveness and read speed
2Device complexity
If a fixed sequence of read-level voltages is used for multi-stage decoding operations, then device complexity is reduced, but error recovery efficiency decreases in high-error-rate environments
Solution Approach 1:
The system implements feedback mechanisms where decoding success or failure at each voltage level is recorded and used to influence subsequent read attempts. The history of successful decoding voltages is fed back into the system to guide future read operations, creating an adaptive loop that improves error recovery efficiency without requiring complex real-time analysis
Solution Approach 2:
The system changes operational parameters (read-level voltages and their sequence) based on historical performance data. By analyzing patterns in previously successful decodings, the system adjusts voltage levels and ordering to match current error conditions, thereby improving error recovery efficiency while maintaining relatively simple device architecture
Data Source
AI summary
Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.