NAND Flash Read Threshold Calibration via ECC Bit Error Rate Analysis
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Solution Overview
Problem
The challenge in memory systems is maintaining process uniformity and variability across memory dies, blocks, and pages under diverse conditions, which requires adaptive systems to track optimal read thresholds effectively, especially in NAND process shrinking and 3D stacking, where existing methods incur high latency penalties due to multiple read operations for calibration.
Innovation Solution
A method and system that calibrate read threshold voltages by receiving page bits from memory dies, determining voltage bins, calculating bit error rates, and adjusting read threshold voltages using a Gaussian tail distribution function, thereby reducing the number of read operations required for calibration and improving latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple read operations are performed for calibration to track optimal read thresholds, then the accuracy of read threshold calibration is improved, but the latency increases
Solution Approach 1:
The patent extracts only the essential information needed for calibration by reading data bits once and using ECC syndrome analysis to determine bit error rates, rather than performing multiple read operations. This extraction approach maintains calibration accuracy while significantly reducing the number of read operations required.
Solution Approach 2:
The patent replaces the mechanical approach of multiple physical read operations with a computational approach using ECC syndrome analysis and Gaussian tail distribution functions. This substitution allows the system to calculate bit error rates and adjust read thresholds based on mathematical analysis of a single read operation's results, thereby reducing latency while maintaining precision.
2Loss of time
If the number of read operations is reduced for calibration, then the latency is reduced, but the accuracy of read threshold calibration may deteriorate
Solution Approach 1:
The patent implements feedback by using ECC syndrome analysis to detect bit errors in the read data, calculating bit error rates, and using this feedback information to adjust read threshold voltages. This closed-loop feedback mechanism ensures that even with a single read operation, the system can accurately determine the optimal read thresholds by continuously monitoring and adjusting based on error rates.
Solution Approach 2:
The patent changes the parameter being measured from raw data accuracy to bit error rate derived from ECC syndromes. By analyzing the syndrome patterns and applying Gaussian tail distribution functions, the system can infer the underlying voltage distribution characteristics and determine optimal thresholds without requiring multiple reads, thus maintaining precision while reducing time loss.
3Reliability
If adaptive tracking of read thresholds is implemented for each memory die, then the Quality of Service is improved, but the device complexity increases
Solution Approach 1:
The patent implements a universal calibration approach that can be applied across all memory dies using the same ECC syndrome analysis methodology. The controller performs bit error rate analysis and read threshold adjustment for each die independently, but uses the same underlying algorithm and mathematical models, thereby improving QoS across the system without proportionally increasing complexity.
Solution Approach 2:
The system enables each memory die to be self-calibrated through automated bit error rate analysis and threshold adjustment performed by the controller. The process autonomously monitors read errors, calculates appropriate threshold adjustments using Gaussian tail distribution, and applies corrections without manual intervention, thereby improving reliability while keeping the complexity manageable through automation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances read throughput and Quality of Service (QoS) by reducing latency and improving the accuracy of read threshold calibration, especially in multi-level cell (MLC) storage schemes, while maintaining efficient performance across varying conditions.
Implementation Method 1
adjust read threshold voltages associated with the at least one memory die using a Gaussian tail distribution function and the bit error rate for each voltage bin
Data Source
AI summary
A method for calibrating read threshold voltages includes receiving, from at least one memory die, a number of page bits corresponding to a number of read operations performed on a page associated with the at least one memory die. The method further includes determining voltage bins for each bit of the number of page bits. The method further includes determining, for each voltage bin, a bit error rate. The method further includes adjusting read threshold voltages associated with the at least one memory die using the bite error rate for each voltage bin.