NAND Memory Controller Read-Voltage Adaptation for Error Recovery

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

NAND flash memory systems face reading errors due to changes in the charge distribution in floating gates, leading to suboptimal read voltages and increased error rates from factors like data retention errors and read disturb defects.

Innovation Solution

A memory system with a memory controller that performs dual readings using a hard decision voltage and multiple voltages within a predetermined range, calculates and updates the optimal read voltage, and stores this value for subsequent use, enabling improved decoding through likelihood information and reducing reading errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed read voltage is used for reading NAND flash memory, then the reading process is simple and fast, but reading errors increase due to charge distribution changes in floating gates

Engineering Contradiction:
Improvereading accuracyVSAvoidreading process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary distribution reading at multiple voltages to determine the optimal read voltage before actual data reading. This preliminary action updates the hard decision voltage to match the current charge distribution state, thereby improving reading accuracy without making the main reading process complex.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically changes the read voltage parameter based on the detected charge distribution. By updating the hard decision voltage according to the distribution reading results, the system adapts to charge distribution changes and maintains high reading accuracy.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple read voltages are applied to determine optimal read voltage, then reading accuracy improves, but the number of readings increases and time is consumed

Engineering Contradiction:
Improvereading accuracyVSAvoidreading time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The distribution reading to determine optimal voltage is performed as a preliminary step before actual data reading. This allows the system to prepare the correct read voltage in advance, ensuring accurate reading without repeated attempts and reducing overall time loss.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses feedback from distribution reading results to update the hard decision voltage. This feedback mechanism ensures that the optimal voltage is identified and applied, improving reading accuracy while minimizing the number of readings needed.

Inventive Principle:
Principle #23Feedback

3Reliability

If distribution reading is performed to update hard decision voltage, then reading errors are reduced, but device operation becomes more complex

Engineering Contradiction:
Improvereading reliabilityVSAvoidoperation simplicity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The memory controller automatically performs distribution reading and updates the hard decision voltage without requiring external intervention. This self-service mechanism maintains high reading reliability while keeping the operation simple for the user.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The memory controller integrates multiple functions including distribution reading, voltage determination, and data reading into a single device. This multi-functionality reduces the need for external equipment and simplifies the overall operation while maintaining high reading reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10320429B2Memory controller, memory system and memory control method
Publication Date: 2019.06.11 KIOXIA CORP
  • US10320429B2 patent drawing
  • US10320429B2 patent drawing
  • US10320429B2 patent drawing

AI summary

According to the embodiment, a memory controller includes a memory interface which performs a first reading using a read voltage including a hard decision voltage and a second reading using a plurality of read voltages within a predetermined voltage range, a shift value calculation unit which calculates an update value of the hard decision voltage based on the reading result by the second reading, a storage unit which stores the update value, a decoding unit which performs decoding based on likelihood information according to the reading result, and a controller which makes the memory controller perform the first reading, makes the decoding unit perform the decoding by using the likelihood information using a reading result by the second reading when the decoding has been failed, and makes the memory controller perform the first reading by using the update value when the corresponding update value is stored in the storage unit.